[S/390]: DFA description for z900.
Hartmut Penner
hpenner@de.ibm.com
Wed Jan 15 10:35:00 GMT 2003
Hello,
I will commit the DFA description for the z900.
Bootstrapped on s390x.
* config/s390/s390.c (s390_safe_attr_type): New function.
(s390_use_dfa_pipeline_interface): New function, return true for z900.
(s390_issue_rate): New function.
(s390_agen_dep_p): New function.
(addr_generation_dependency_p): Use 's390_safe_attr_type'.
(s390_adjust_cost): Return 'cost' if new DFA is used.
(s390_adjust_priority): Delete function.
* config/s390/s390-protos.h: (s390_agen_dep_p): New prototype.
* config/s390/s390.md (atype attribute): Attribute 'atype' default
determined by 'op_type'.
(type attribute): Added more type attributes.
* config/s390/2064.md: New DFA description for z900 pipeline.
New file 2064.md:
;; Scheduling description for z900 (cpu 2064).
;; Copyright (C) 2002 Free Software Foundation, Inc.
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
;;
;; This file is part of GNU CC.
;;
;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
;; any later version.
;;
;; GNU CC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GNU CC; see the file COPYING. If not, write to
;; the Free Software Foundation, 59 Temple Place - Suite 330,
;; Boston, MA 02111-1307, USA.
;;
;; References:
;; The microarchitecture of the IBM eServer z900 processor.
;; E.M. Schwarz et al.
;; IBM Journal of Research and Development Vol. 46 No 4/5, 2002.
;;
;; z900 (cpu 2064) pipeline
;;
;; dec
;; --> | <---
;; LA bypass | agen |
;; | | |
;; --- c1 | Load bypass
;; | |
;; c2----
;; |
;; e1
;; |
;; wr
(define_automaton "z_ipu")
(define_cpu_unit "z_e1" "z_ipu")
(define_cpu_unit "z_wr" "z_ipu")
(define_insn_reservation "z_la" 1
(and (eq_attr "cpu" "z900")
(eq_attr "type" "la"))
"z_e1,z_wr")
(define_insn_reservation "z_larl" 1
(and (eq_attr "cpu" "z900")
(eq_attr "type" "larl"))
"z_e1,z_wr")
(define_insn_reservation "z_load" 1
(and (eq_attr "cpu" "z900")
(eq_attr "type" "load"))
"z_e1,z_wr")
(define_insn_reservation "z_store" 1
(and (eq_attr "cpu" "z900")
(eq_attr "type" "store"))
"z_e1,z_wr")
(define_insn_reservation "z_call" 5
(and (eq_attr "cpu" "z900")
(eq_attr "type" "jsr"))
"z_e1*5,z_wr")
(define_insn_reservation "z_o2" 2
(and (eq_attr "cpu" "z900")
(eq_attr "type" "o2"))
"z_e1*2,z_wr")
(define_insn_reservation "z_o3" 3
(and (eq_attr "cpu" "z900")
(eq_attr "type" "o3"))
"z_e1*3,z_wr")
;
; Insn still not mentioned are check for
; the usage of the agen unit
;
(define_insn_reservation "z_int" 1
(and (eq_attr "cpu" "z900")
(eq_attr "atype" "reg"))
"z_e1,z_wr")
(define_insn_reservation "z_agen" 1
(and (eq_attr "cpu" "z900")
(eq_attr "atype" "agen"))
"z_e1,z_wr")
;;
;; s390_agen_dep_p returns 1, if a register is set in the
;; first insn and used in the dependend insn to form a address.
;;
;;
;; If a intruction uses a register to address memory, it needs
;; to be set 5 cycles in advance.
;;
(define_bypass 5 "z_int,z_agen"
"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
;;
;; A load type instruction uses a bypass to feed the result back
;; to the address generation pipeline stage.
;;
(define_bypass 2 "z_load"
"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
;;
;; A load address type instruction uses a bypass to feed the
;; result back to the address generation pipeline stage.
;;
(define_bypass 1 "z_larl,z_la"
"z_agen,z_la,z_call,z_load,z_store" "s390_agen_dep_p")
Index: config/s390/s390-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390-protos.h,v
retrieving revision 1.21
diff -c -p -r1.21 s390-protos.h
*** config/s390/s390-protos.h 26 Nov 2002 15:26:39 -0000 1.21
--- config/s390/s390-protos.h 15 Jan 2003 10:21:34 -0000
*************** extern void s390_initialize_trampoline P
*** 76,81 ****
--- 76,83 ----
extern rtx s390_gen_rtx_const_DI PARAMS ((int, int));
extern rtx s390_simplify_dwarf_addr PARAMS ((rtx));
extern void s390_machine_dependent_reorg PARAMS ((rtx));
+ extern int s390_agen_dep_p PARAMS ((rtx, rtx));
+
#endif /* RTX_CODE */
#ifdef TREE_CODE
Index: config/s390/s390.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.c,v
retrieving revision 1.74
diff -c -p -r1.74 s390.c
*** config/s390/s390.c 10 Jan 2003 15:17:14 -0000 1.74
--- config/s390/s390.c 15 Jan 2003 10:21:37 -0000
*************** Boston, MA 02111-1307, USA. */
*** 51,63 ****
#include "optabs.h"
static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int));
- static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int));
- static int s390_adjust_priority PARAMS ((rtx, int));
static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx,
unsigned HOST_WIDE_INT));
static void s390_encode_section_info PARAMS ((tree, int));
static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree));
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
--- 51,67 ----
#include "optabs.h"
static bool s390_assemble_integer PARAMS ((rtx, unsigned int, int));
static void s390_select_rtx_section PARAMS ((enum machine_mode, rtx,
unsigned HOST_WIDE_INT));
static void s390_encode_section_info PARAMS ((tree, int));
static void s390_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
HOST_WIDE_INT, tree));
+ static enum attr_type s390_safe_attr_type PARAMS ((rtx));
+
+ static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int));
+ static int s390_issue_rate PARAMS ((void));
+ static int s390_use_dfa_pipeline_interface PARAMS ((void));
+
#undef TARGET_ASM_ALIGNED_HI_OP
#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
*************** static void s390_output_mi_thunk PARAMS
*** 75,86 ****
#undef TARGET_ASM_SELECT_RTX_SECTION
#define TARGET_ASM_SELECT_RTX_SECTION s390_select_rtx_section
- #undef TARGET_SCHED_ADJUST_COST
- #define TARGET_SCHED_ADJUST_COST s390_adjust_cost
-
- #undef TARGET_SCHED_ADJUST_PRIORITY
- #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
-
#undef TARGET_ENCODE_SECTION_INFO
#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
--- 79,84 ----
*************** static void s390_output_mi_thunk PARAMS
*** 89,94 ****
--- 87,100 ----
#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
+ #undef TARGET_SCHED_ADJUST_COST
+ #define TARGET_SCHED_ADJUST_COST s390_adjust_cost
+ #undef TARGET_SCHED_ISSUE_RATE
+ #define TARGET_SCHED_ISSUE_RATE s390_issue_rate
+ #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+ #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
s390_use_dfa_pipeline_interface
+
+
struct gcc_target targetm = TARGET_INITIALIZER;
extern int reload_completed;
*************** const enum reg_class regclass_map[FIRST_
*** 936,941 ****
--- 942,958 ----
ADDR_REGS, NO_REGS, ADDR_REGS
};
+ /* Return attribute type of insn. */
+
+ static enum attr_type
+ s390_safe_attr_type (insn)
+ rtx insn;
+ {
+ if (recog_memoized (insn) >= 0)
+ return get_attr_type (insn);
+ else
+ return TYPE_NONE;
+ }
/* Return true if OP a (const_int 0) operand.
OP is the current operation.
*************** s390_assemble_integer (x, size, aligned_
*** 2892,2900 ****
return default_assemble_integer (x, size, aligned_p);
}
-
- #define DEBUG_SCHED 0
-
/* Returns true if register REGNO is used for forming
a memory address in expression X. */
--- 2909,2914 ----
*************** addr_generation_dependency_p (dep_rtx, i
*** 2946,2951 ****
--- 2960,2968 ----
{
rtx target, pat;
+ if (GET_CODE (dep_rtx) == INSN)
+ dep_rtx = PATTERN (dep_rtx);
+
if (GET_CODE (dep_rtx) == SET)
{
target = SET_DEST (dep_rtx);
*************** addr_generation_dependency_p (dep_rtx, i
*** 2958,2964 ****
{
int regno = REGNO (target);
! if (get_attr_type (insn) == TYPE_LA)
{
pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL)
--- 2975,2981 ----
{
int regno = REGNO (target);
! if (s390_safe_attr_type (insn) == TYPE_LA)
{
pat = PATTERN (insn);
if (GET_CODE (pat) == PARALLEL)
*************** addr_generation_dependency_p (dep_rtx, i
*** 2972,2984 ****
else
abort();
}
! else if (get_attr_atype (insn) == ATYPE_MEM)
return reg_used_in_mem_p (regno, PATTERN (insn));
}
}
return 0;
}
/* Return the modified cost of the dependency of instruction INSN
on instruction DEP_INSN through the link LINK. COST is the
--- 2989,3026 ----
else
abort();
}
! else if (get_attr_atype (insn) == ATYPE_AGEN)
return reg_used_in_mem_p (regno, PATTERN (insn));
}
}
return 0;
}
+ /* Return 1, if dep_insn sets register used in insn in the agen unit. */
+
+
+ int
+ s390_agen_dep_p(dep_insn, insn)
+ rtx dep_insn;
+ rtx insn;
+ {
+ rtx dep_rtx = PATTERN (dep_insn);
+ int i;
+
+ if (GET_CODE (dep_rtx) == SET
+ && addr_generation_dependency_p (dep_rtx, insn))
+ return 1;
+ else if (GET_CODE (dep_rtx) == PARALLEL)
+ {
+ for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
+ {
+ if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
+ return 1;
+ }
+ }
+ return 0;
+ }
+
/* Return the modified cost of the dependency of instruction INSN
on instruction DEP_INSN through the link LINK. COST is the
*************** s390_adjust_cost (insn, link, dep_insn,
*** 3012,3098 ****
if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
return cost;
dep_rtx = PATTERN (dep_insn);
! if (GET_CODE (dep_rtx) == SET)
! {
! if (addr_generation_dependency_p (dep_rtx, insn))
! {
! cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
! if (DEBUG_SCHED)
! {
! fprintf (stderr, "\n\nAddress dependency detected: cost %d\n",
! cost);
! debug_rtx (dep_insn);
! debug_rtx (insn);
! }
! }
! }
else if (GET_CODE (dep_rtx) == PARALLEL)
{
for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
{
! if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i),
! insn))
! {
! cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
! if (DEBUG_SCHED)
! {
! fprintf (stderr, "\n\nAddress dependency detected: cost %d\n"
! ,cost);
! debug_rtx (dep_insn);
! debug_rtx (insn);
! }
! }
}
}
return cost;
}
! /* A C statement (sans semicolon) to update the integer scheduling priority
! INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier,
! increase the priority to execute INSN later. Do not define this macro if
! you do not need to adjust the scheduling priorities of insns.
! A LA instruction maybe scheduled later, since the pipeline bypasses the
! calculated value. */
static int
! s390_adjust_priority (insn, priority)
! rtx insn ATTRIBUTE_UNUSED;
! int priority;
! {
! if (! INSN_P (insn))
! return priority;
!
! if (GET_CODE (PATTERN (insn)) == USE
! || GET_CODE (PATTERN (insn)) == CLOBBER)
! return priority;
!
! switch (get_attr_type (insn))
! {
! default:
! break;
!
! case TYPE_LA:
! if (priority >= 0 && priority < 0x01000000)
! priority <<= 3;
! break;
! case TYPE_LM:
! /* LM in epilogue should never be scheduled. This
! is due to literal access done in function body.
! The usage of register 13 is not mentioned explicitly,
! leading to scheduling 'LM' accross this instructions.
! */
! priority = 0x7fffffff;
! break;
! }
!
! return priority;
! }
/* Split all branches that exceed the maximum distance.
Returns true if this created a new literal pool entry.
--- 3054,3099 ----
if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
return cost;
+ /* DFA based scheduling checks address dependency in md file. */
+ if (s390_use_dfa_pipeline_interface ())
+ return cost;
+
dep_rtx = PATTERN (dep_insn);
! if (GET_CODE (dep_rtx) == SET
! && addr_generation_dependency_p (dep_rtx, insn))
! cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
else if (GET_CODE (dep_rtx) == PARALLEL)
{
for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
{
! if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
! cost += (s390_safe_attr_type (dep_insn) == TYPE_LA) ? 1 : 4;
}
}
return cost;
}
+ /* The number of instructions that can be issued per cycle. */
! static int
! s390_issue_rate ()
! {
! return 1;
! }
! /* If the following function returns TRUE, we will use the the DFA
! insn scheduler. */
static int
! s390_use_dfa_pipeline_interface ()
! {
! if (s390_cpu == PROCESSOR_2064_Z900)
! return 1;
! return 0;
+ }
/* Split all branches that exceed the maximum distance.
Returns true if this created a new literal pool entry.
Index: config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.44
diff -c -p -r1.44 s390.md
*** config/s390/s390.md 20 Dec 2002 13:02:42 -0000 1.44
--- config/s390/s390.md 15 Jan 2003 10:21:41 -0000
***************
*** 3,9 ****
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
;; This file is part of GNU CC.
!
;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
--- 3,9 ----
;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
;; Ulrich Weigand (uweigand@de.ibm.com).
;; This file is part of GNU CC.
!
;; GNU CC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 2, or (at your option)
***************
*** 53,67 ****
;; Define an insn type attribute. This is used in function unit delay
;; computations.
! (define_attr "type"
"none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3"
! (const_string "integer"))
;; Insn are devide in two classes:
! ;; mem: Insn accessing memory
! ;; reg: Insn operands all in registers
! (define_attr "atype" "reg,mem"
! (const_string "reg"))
;; Generic pipeline function unit.
--- 53,93 ----
;; Define an insn type attribute. This is used in function unit delay
;; computations.
! (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
! cs,vs,store,imul,idiv,
! branch,jsr,fsimpd,fsimps,
! floadd,floads,fstored, fstores,
! fmuld,fmuls,fdivd,fdivs,
! ftoi,itof,fsqrtd,fsqrts,
! other,o2,o3"
! (const_string "integer"))
!
! ;; Operand type. Used to default length attribute values
!
! (define_attr "op_type"
! "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
! (const_string "RX"))
;; Insn are devide in two classes:
! ;; agen: Insn using agen
! ;; reg: Insn not using agen
! (define_attr "atype" "agen,reg"
! (cond [ (eq_attr "op_type" "E") (const_string "reg")
! (eq_attr "op_type" "RR") (const_string "reg")
! (eq_attr "op_type" "RX") (const_string "agen")
! (eq_attr "op_type" "RI") (const_string "reg")
! (eq_attr "op_type" "RRE") (const_string "reg")
! (eq_attr "op_type" "RS") (const_string "agen")
! (eq_attr "op_type" "RSI") (const_string "agen")
! (eq_attr "op_type" "S") (const_string "agen")
! (eq_attr "op_type" "SI") (const_string "agen")
! (eq_attr "op_type" "SS") (const_string "agen")
! (eq_attr "op_type" "SSE") (const_string "agen")
! (eq_attr "op_type" "RXE") (const_string "agen")
! (eq_attr "op_type" "RSE") (const_string "agen")
! (eq_attr "op_type" "RIL") (const_string "agen")]
! (const_string "reg")))
;; Generic pipeline function unit.
***************
*** 72,89 ****
--- 98,139 ----
(eq_attr "type" "integer") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "fsimpd") 1 1)
+
+ (define_function_unit "integer" 1 0
+ (eq_attr "type" "fsimps") 1 1)
+
+ (define_function_unit "integer" 1 0
(eq_attr "type" "load") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "floadd") 1 1)
+
+ (define_function_unit "integer" 1 0
+ (eq_attr "type" "floads") 1 1)
+
+ (define_function_unit "integer" 1 0
(eq_attr "type" "la") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "larl") 1 1)
+
+ (define_function_unit "integer" 1 0
(eq_attr "type" "lr") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "branch") 1 1)
+
+ (define_function_unit "integer" 1 0
(eq_attr "type" "store") 1 1)
(define_function_unit "integer" 1 0
+ (eq_attr "type" "fstored") 1 1)
+
+ (define_function_unit "integer" 1 0
+ (eq_attr "type" "fstores") 1 1)
+
+ (define_function_unit "integer" 1 0
(eq_attr "type" "lm") 2 2)
(define_function_unit "integer" 1 0
***************
*** 102,114 ****
(eq_attr "type" "imul") 7 7)
(define_function_unit "integer" 1 0
! (eq_attr "type" "fmul") 6 6)
(define_function_unit "integer" 1 0
(eq_attr "type" "idiv") 33 33)
(define_function_unit "integer" 1 0
! (eq_attr "type" "fdiv") 33 33)
(define_function_unit "integer" 1 0
(eq_attr "type" "o2") 2 2)
--- 152,182 ----
(eq_attr "type" "imul") 7 7)
(define_function_unit "integer" 1 0
! (eq_attr "type" "fmuld") 6 6)
!
! (define_function_unit "integer" 1 0
! (eq_attr "type" "fmuls") 6 6)
(define_function_unit "integer" 1 0
(eq_attr "type" "idiv") 33 33)
(define_function_unit "integer" 1 0
! (eq_attr "type" "fdivd") 33 33)
!
! (define_function_unit "integer" 1 0
! (eq_attr "type" "fdivs") 33 33)
!
! (define_function_unit "integer" 1 0
! (eq_attr "type" "fsqrtd") 30 30)
!
! (define_function_unit "integer" 1 0
! (eq_attr "type" "fsqrts") 30 30)
!
! (define_function_unit "integer" 1 0
! (eq_attr "type" "ftoi") 2 2)
!
! (define_function_unit "integer" 1 0
! (eq_attr "type" "itof") 2 2)
(define_function_unit "integer" 1 0
(eq_attr "type" "o2") 2 2)
***************
*** 119,129 ****
(define_function_unit "integer" 1 0
(eq_attr "type" "other") 5 5)
! ;; Operand type. Used to default length attribute values
! (define_attr "op_type"
! "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE"
! (const_string "RX"))
;; Length in bytes.
--- 187,195 ----
(define_function_unit "integer" 1 0
(eq_attr "type" "other") 5 5)
! ;; Pipeline description for z900
! (include "2064.md")
;; Length in bytes.
***************
*** 135,141 ****
(eq_attr "op_type" "RRE") (const_int 4)
(eq_attr "op_type" "RS") (const_int 4)
(eq_attr "op_type" "RSI") (const_int 4)
- (eq_attr "op_type" "RX") (const_int 4)
(eq_attr "op_type" "S") (const_int 4)
(eq_attr "op_type" "SI") (const_int 4)
(eq_attr "op_type" "SS") (const_int 6)
--- 201,206 ----
***************
*** 298,305 ****
operands[2] = GEN_INT (block << shift);
return \"tm\\t%0,%b2\";
}"
! [(set_attr "op_type" "SI")
! (set_attr "atype" "mem")])
; Test-under-Mask instructions
--- 363,369 ----
operands[2] = GEN_INT (block << shift);
return \"tm\\t%0,%b2\";
}"
! [(set_attr "op_type" "SI")])
; Test-under-Mask instructions
***************
*** 320,327 ****
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI")
! (set_attr "atype" "mem")])
(define_insn "*tmsi_mem"
[(set (reg 33)
--- 384,390 ----
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI")])
(define_insn "*tmsi_mem"
[(set (reg 33)
***************
*** 339,346 ****
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI")
! (set_attr "atype" "mem")])
(define_insn "*tmhi_mem"
[(set (reg 33)
--- 402,408 ----
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI")])
(define_insn "*tmhi_mem"
[(set (reg 33)
***************
*** 358,365 ****
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI")
! (set_attr "atype" "mem")])
(define_insn "*tmqi_mem"
[(set (reg 33)
--- 420,426 ----
plus_constant (XEXP (operands[0], 0), part));
return \"tm\\t%0,%b1\";
}"
! [(set_attr "op_type" "SI")])
(define_insn "*tmqi_mem"
[(set (reg 33)
***************
*** 368,375 ****
(match_operand:SI 2 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"tm\\t%0,%b1"
! [(set_attr "op_type" "SI")
! (set_attr "atype" "mem")])
(define_insn "*tmdi_reg"
[(set (reg 33)
--- 429,435 ----
(match_operand:SI 2 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
"tm\\t%0,%b1"
! [(set_attr "op_type" "SI")])
(define_insn "*tmdi_reg"
[(set (reg 33)
***************
*** 470,476 ****
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
"srda\\t%0,0"
! [(set_attr "op_type" "RS")])
(define_insn "*tstsi"
[(set (reg 33)
--- 530,538 ----
(match_operand:DI 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
"srda\\t%0,0"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
(define_insn "*tstsi"
[(set (reg 33)
***************
*** 482,489 ****
"@
ltr\\t%2,%0
icm\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS")
! (set_attr "atype" "reg,mem")])
(define_insn "*tstsi_cconly"
[(set (reg 33)
--- 544,550 ----
"@
ltr\\t%2,%0
icm\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS")])
(define_insn "*tstsi_cconly"
[(set (reg 33)
***************
*** 494,501 ****
"@
ltr\\t%0,%0
icm\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS")
! (set_attr "atype" "reg,mem")])
(define_insn "*tstsi_cconly2"
[(set (reg 33)
--- 555,561 ----
"@
ltr\\t%0,%0
icm\\t%2,15,%0"
! [(set_attr "op_type" "RR,RS")])
(define_insn "*tstsi_cconly2"
[(set (reg 33)
***************
*** 515,522 ****
"@
icm\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RI")
! (set_attr "atype" "mem,reg")])
(define_insn "*tsthiCCT_cconly"
[(set (reg 33)
--- 575,581 ----
"@
icm\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RI")])
(define_insn "*tsthiCCT_cconly"
[(set (reg 33)
***************
*** 527,534 ****
"@
icm\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RI")
! (set_attr "atype" "mem,reg")])
(define_insn "*tsthi"
[(set (reg 33)
--- 586,592 ----
"@
icm\\t%2,3,%0
tml\\t%0,65535"
! [(set_attr "op_type" "RS,RI")])
(define_insn "*tsthi"
[(set (reg 33)
***************
*** 538,545 ****
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn "*tsthi_cconly"
[(set (reg 33)
--- 596,602 ----
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0"
! [(set_attr "op_type" "RS")])
(define_insn "*tsthi_cconly"
[(set (reg 33)
***************
*** 548,555 ****
(clobber (match_scratch:HI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn "*tstqiCCT"
[(set (reg 33)
--- 605,611 ----
(clobber (match_scratch:HI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,3,%0"
! [(set_attr "op_type" "RS")])
(define_insn "*tstqiCCT"
[(set (reg 33)
***************
*** 561,568 ****
"@
icm\\t%2,1,%0
tml\\t%0,255"
! [(set_attr "op_type" "RS,RI")
! (set_attr "atype" "mem,reg")])
(define_insn "*tstqiCCT_cconly"
[(set (reg 33)
--- 617,623 ----
"@
icm\\t%2,1,%0
tml\\t%0,255"
! [(set_attr "op_type" "RS,RI")])
(define_insn "*tstqiCCT_cconly"
[(set (reg 33)
***************
*** 572,579 ****
"@
cli\\t%0,0
tml\\t%0,255"
! [(set_attr "op_type" "SI,RI")
! (set_attr "atype" "mem,reg")])
(define_insn "*tstqi"
[(set (reg 33)
--- 627,633 ----
"@
cli\\t%0,0
tml\\t%0,255"
! [(set_attr "op_type" "SI,RI")])
(define_insn "*tstqi"
[(set (reg 33)
***************
*** 583,590 ****
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn "*tstqi_cconly"
[(set (reg 33)
--- 637,643 ----
(match_dup 0))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0"
! [(set_attr "op_type" "RS")])
(define_insn "*tstqi_cconly"
[(set (reg 33)
***************
*** 593,601 ****
(clobber (match_scratch:QI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
!
; Compare (signed) instructions
--- 646,652 ----
(clobber (match_scratch:QI 2 "=d"))]
"s390_match_ccmode(insn, CCSmode)"
"icm\\t%2,1,%0"
! [(set_attr "op_type" "RS")])
; Compare (signed) instructions
***************
*** 607,614 ****
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*cmpdi_ccs"
[(set (reg 33)
--- 658,664 ----
"@
cgfr\\t%0,%1
cgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpdi_ccs"
[(set (reg 33)
***************
*** 619,626 ****
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
! [(set_attr "op_type" "RRE,RI,RXE")
! (set_attr "atype" "reg,reg,mem")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
--- 669,675 ----
cgr\\t%0,%1
cghi\\t%0,%c1
cg\\t%0,%1"
! [(set_attr "op_type" "RRE,RI,RXE")])
(define_insn "*cmpsi_ccs_sign"
[(set (reg 33)
***************
*** 628,635 ****
(match_operand:SI 0 "register_operand" "d")))]
"s390_match_ccmode(insn, CCSRmode)"
"ch\\t%0,%1"
! [(set_attr "op_type" "RX")
! (set_attr "atype" "mem")])
(define_insn "*cmpsi_ccs"
[(set (reg 33)
--- 677,683 ----
(match_operand:SI 0 "register_operand" "d")))]
"s390_match_ccmode(insn, CCSRmode)"
"ch\\t%0,%1"
! [(set_attr "op_type" "RX")])
(define_insn "*cmpsi_ccs"
[(set (reg 33)
***************
*** 640,647 ****
cr\\t%0,%1
chi\\t%0,%c1
c\\t%0,%1"
! [(set_attr "op_type" "RR,RI,RX")
! (set_attr "atype" "reg,reg,mem")])
; Compare (unsigned) instructions
--- 688,694 ----
cr\\t%0,%1
chi\\t%0,%c1
c\\t%0,%1"
! [(set_attr "op_type" "RR,RI,RX")])
; Compare (unsigned) instructions
***************
*** 654,661 ****
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*cmpdi_ccu"
[(set (reg 33)
--- 701,707 ----
"@
clgfr\\t%0,%1
clgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpdi_ccu"
[(set (reg 33)
***************
*** 665,672 ****
"@
clgr\\t%0,%1
clg\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*cmpsi_ccu"
[(set (reg 33)
--- 711,717 ----
"@
clgr\\t%0,%1
clg\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*cmpsi_ccu"
[(set (reg 33)
***************
*** 676,683 ****
"@
clr\\t%0,%1
cl\\t%0,%1"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*cmphi_ccu"
[(set (reg 33)
--- 721,727 ----
"@
clr\\t%0,%1
cl\\t%0,%1"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*cmphi_ccu"
[(set (reg 33)
***************
*** 685,692 ****
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,3,%1"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn "*cmpqi_ccu"
[(set (reg 33)
--- 729,735 ----
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,3,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*cmpqi_ccu"
[(set (reg 33)
***************
*** 694,701 ****
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,1,%1"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn "*cli"
[(set (reg 33)
--- 737,743 ----
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clm\\t%0,1,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*cli"
[(set (reg 33)
***************
*** 703,710 ****
(match_operand:QI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, CCUmode)"
"cli\\t%0,%b1"
! [(set_attr "op_type" "SI")
! (set_attr "atype" "mem")])
(define_insn "*cmpdi_ccu_mem"
[(set (reg 33)
--- 745,751 ----
(match_operand:QI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, CCUmode)"
"cli\\t%0,%b1"
! [(set_attr "op_type" "SI")])
(define_insn "*cmpdi_ccu_mem"
[(set (reg 33)
***************
*** 712,719 ****
(match_operand:DI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*cmpsi_ccu_mem"
[(set (reg 33)
--- 753,759 ----
(match_operand:DI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*cmpsi_ccu_mem"
[(set (reg 33)
***************
*** 721,728 ****
(match_operand:SI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*cmphi_ccu_mem"
[(set (reg 33)
--- 761,767 ----
(match_operand:SI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*cmphi_ccu_mem"
[(set (reg 33)
***************
*** 730,737 ****
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*cmpqi_ccu_mem"
[(set (reg 33)
--- 769,775 ----
(match_operand:HI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*cmpqi_ccu_mem"
[(set (reg 33)
***************
*** 739,746 ****
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
; DF instructions
--- 777,783 ----
(match_operand:QI 1 "s_imm_operand" "Q")))]
"s390_match_ccmode(insn, CCUmode)"
"clc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SS")])
; DF instructions
***************
*** 751,757 ****
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
"ltdbr\\t%0,%0"
! [(set_attr "op_type" "RRE")])
(define_insn "*cmpdf_ccs_0_ibm"
[(set (reg 33)
--- 788,795 ----
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
"ltdbr\\t%0,%0"
! [(set_attr "op_type" "RRE")
! (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs_0_ibm"
[(set (reg 33)
***************
*** 759,765 ****
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IBM_FLOAT"
"ltdr\\t%0,%0"
! [(set_attr "op_type" "RR")])
(define_insn "*cmpdf_ccs"
[(set (reg 33)
--- 797,804 ----
(match_operand:DF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IBM_FLOAT"
"ltdr\\t%0,%0"
! [(set_attr "op_type" "RR")
! (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs"
[(set (reg 33)
***************
*** 770,776 ****
cdbr\\t%0,%1
cdb\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
--- 809,815 ----
cdbr\\t%0,%1
cdb\\t%0,%1"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fsimpd")])
(define_insn "*cmpdf_ccs_ibm"
[(set (reg 33)
***************
*** 781,787 ****
cdr\\t%0,%1
cd\\t%0,%1"
[(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
; SF instructions
--- 820,826 ----
cdr\\t%0,%1
cd\\t%0,%1"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fsimpd")])
; SF instructions
***************
*** 792,798 ****
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
"ltebr\\t%0,%0"
! [(set_attr "op_type" "RRE")])
(define_insn "*cmpsf_ccs_0_ibm"
[(set (reg 33)
--- 831,838 ----
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IEEE_FLOAT"
"ltebr\\t%0,%0"
! [(set_attr "op_type" "RRE")
! (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs_0_ibm"
[(set (reg 33)
***************
*** 800,806 ****
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IBM_FLOAT"
"lter\\t%0,%0"
! [(set_attr "op_type" "RR")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
--- 840,847 ----
(match_operand:SF 1 "const0_operand" "")))]
"s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT &&
TARGET_IBM_FLOAT"
"lter\\t%0,%0"
! [(set_attr "op_type" "RR")
! (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
***************
*** 810,817 ****
"@
cebr\\t%0,%1
ceb\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
--- 851,858 ----
"@
cebr\\t%0,%1
ceb\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fsimps")])
(define_insn "*cmpsf_ccs"
[(set (reg 33)
***************
*** 821,828 ****
"@
cer\\t%0,%1
ce\\t%0,%1"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
;;
--- 862,869 ----
"@
cer\\t%0,%1
ce\\t%0,%1"
! [(set_attr "op_type" "RR,RX")
! (set_attr "type" "fsimps")])
;;
***************
*** 843,850 ****
#
#
mvc\\t%O0(16,%R0),%1"
! [(set_attr "op_type" "RSE,RSE,NN,NN,SS")
! (set_attr "atype" "mem")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
--- 884,890 ----
#
#
mvc\\t%O0(16,%R0),%1"
! [(set_attr "op_type" "RSE,RSE,NN,NN,SS")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
***************
*** 928,935 ****
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
&& !FP_REG_P (operands[0])"
"lghi\\t%0,%h1"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "*movdi_lli"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 968,974 ----
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K')
&& !FP_REG_P (operands[0])"
"lghi\\t%0,%h1"
! [(set_attr "op_type" "RI")])
(define_insn "*movdi_lli"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 950,957 ****
default: abort ();
}
}"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 989,995 ----
default: abort ();
}
}"
! [(set_attr "op_type" "RI")])
(define_insn "*movdi_larl"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 960,967 ****
&& !FP_REG_P (operands[0])"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
! (set_attr "atype" "reg")
! (set_attr "type" "la")])
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
--- 998,1004 ----
&& !FP_REG_P (operands[0])"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
! (set_attr "type" "larl")])
(define_insn "*movdi_64"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!m,Q")
***************
*** 976,982 ****
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
! (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
--- 1013,1019 ----
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RRE,RXE,RXE,RR,RX,RX,SS")
! (set_attr "type" "lr,load,store,floadd,floadd,fstored,cs")])
(define_insn "*movdi_31"
[(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,!*f,!*f,!m,Q")
***************
*** 992,998 ****
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
! (set_attr "atype" "mem,mem,*,*,reg,mem,mem,mem")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
--- 1029,1035 ----
std\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX,SS")
! (set_attr "type" "lm,stm,*,*,floadd,floadd,fstored,cs")])
(define_split
[(set (match_operand:DI 0 "nonimmediate_operand" "")
***************
*** 1138,1144 ****
ste\\t%1,%0
mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
! (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
--- 1175,1181 ----
ste\\t%1,%0
mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
! (set_attr "type" "lr,load,store,floads,floads,fstores,cs")])
(define_peephole2
[(set (match_operand:SI 0 "register_operand" "")
***************
*** 1165,1172 ****
lh\\t%0,%1
sth\\t%1,%0
mvc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RX,SS")
! (set_attr "atype" "reg,reg,mem,mem,mem")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
--- 1202,1208 ----
lh\\t%0,%1
sth\\t%1,%0
mvc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RX,SS")])
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
***************
*** 1194,1201 ****
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
! (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
!
(define_insn "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
--- 1230,1236 ----
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
[(set_attr "op_type" "RR,RI,RXE,RX,SI,SS")
! (set_attr "type" "lr,*,*,store,store,cs")])
(define_insn "movqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q,Q")
***************
*** 1208,1215 ****
stc\\t%1,%0
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")
! (set_attr "atype" "reg,reg,mem,mem,mem,mem")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
--- 1243,1249 ----
stc\\t%1,%0
mvi\\t%0,%b1
mvc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "RR,RI,RX,RX,SI,SS")])
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
***************
*** 1230,1237 ****
(match_operand:QI 1 "memory_operand" "m"))]
""
"ic\\t%0,%1"
! [(set_attr "op_type" "RX")
! (set_attr "atype" "mem")])
;
; movstricthi instruction pattern(s).
--- 1264,1270 ----
(match_operand:QI 1 "memory_operand" "m"))]
""
"ic\\t%0,%1"
! [(set_attr "op_type" "RX")])
;
; movstricthi instruction pattern(s).
***************
*** 1243,1250 ****
(clobber (reg:CC 33))]
""
"icm\\t%0,3,%1"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
;
--- 1276,1282 ----
(clobber (reg:CC 33))]
""
"icm\\t%0,3,%1"
! [(set_attr "op_type" "RS")])
;
***************
*** 1259,1265 ****
lr\\t%0,%1
l\\t%0,%1"
[(set_attr "op_type" "RR,RS")
! (set_attr "atype" "reg,mem")])
;
--- 1291,1297 ----
lr\\t%0,%1
l\\t%0,%1"
[(set_attr "op_type" "RR,RS")
! (set_attr "type" "lr,load")])
;
***************
*** 1292,1298 ****
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
! (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
(define_insn "*movdf_31"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
--- 1324,1330 ----
stg\\t%1,%0
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RRE,RXE,RXE,SS")
! (set_attr "type" "floadd,floadd,fstored,lr,load,store,cs")])
(define_insn "*movdf_31"
[(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m,Q")
***************
*** 1308,1314 ****
#
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
! (set_attr "atype" "reg,mem,mem,mem,mem,*,*,mem")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
--- 1340,1346 ----
#
mvc\\t%O0(8,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN,SS")
! (set_attr "type" "floadd,floadd,fstored,lm,stm,*,*,cs")])
(define_split
[(set (match_operand:DF 0 "nonimmediate_operand" "")
***************
*** 1392,1398 ****
st\\t%1,%0
mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
! (set_attr "atype" "reg,mem,mem,reg,mem,mem,mem")])
;
; load_multiple pattern(s).
--- 1424,1430 ----
st\\t%1,%0
mvc\\t%O0(4,%R0),%1"
[(set_attr "op_type" "RR,RX,RX,RR,RX,RX,SS")
! (set_attr "type" "floads,floads,fstores,lr,load,store,cs")])
;
; load_multiple pattern(s).
***************
*** 1474,1480 ****
return \"lmg\\t%1,%0,%2\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "lm")])
(define_insn "*load_multiple_si"
--- 1506,1511 ----
***************
*** 1493,1499 ****
return \"lm\\t%1,%0,%2\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "lm")])
;
--- 1524,1529 ----
***************
*** 1578,1584 ****
return \"stmg\\t%2,%0,%1\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "stm")])
--- 1608,1613 ----
***************
*** 1598,1604 ****
return \"stm\\t%2,%0,%1\";
}"
[(set_attr "op_type" "RXE")
- (set_attr "atype" "mem")
(set_attr "type" "stm")])
;;
--- 1627,1632 ----
***************
*** 1652,1658 ****
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "mem,mem")
(set_attr "length" "*,14")])
(define_insn "movstr_short_31"
--- 1680,1686 ----
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "movstr_short_31"
***************
*** 1679,1685 ****
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "mem,mem")
(set_attr "length" "*,14")])
; Move a block of arbitrary length.
--- 1707,1713 ----
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Move a block of arbitrary length.
***************
*** 1700,1706 ****
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
- (set_attr "atype" "mem")
(set_attr "length" "8")])
(define_insn "movstr_long_31"
--- 1728,1733 ----
***************
*** 1719,1725 ****
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
(set_attr "type" "vs")
- (set_attr "atype" "mem")
(set_attr "length" "8")])
;
--- 1746,1751 ----
***************
*** 1770,1776 ****
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "mem,mem")
(set_attr "length" "*,14")])
(define_insn "clrstr_short_31"
--- 1796,1802 ----
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "clrstr_short_31"
***************
*** 1798,1804 ****
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "mem,mem")
(set_attr "length" "*,14")])
; Clear a block of arbitrary length.
--- 1824,1830 ----
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Clear a block of arbitrary length.
***************
*** 1815,1821 ****
"TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
--- 1841,1846 ----
***************
*** 1831,1837 ****
"!TARGET_64BIT"
"mvcle\\t%0,%1,0\;jo\\t.-4"
[(set_attr "op_type" "NN")
- (set_attr "atype" "mem")
(set_attr "type" "vs")
(set_attr "length" "8")])
--- 1856,1861 ----
***************
*** 1887,1893 ****
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "mem,mem")
(set_attr "length" "*,14")])
(define_insn "cmpstr_short_31"
--- 1911,1917 ----
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
(define_insn "cmpstr_short_31"
***************
*** 1915,1921 ****
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "mem,mem")
(set_attr "length" "*,14")])
; Compare a block of arbitrary length.
--- 1939,1945 ----
}"
[(set_attr "op_type" "SS,NN")
(set_attr "type" "cs,cs")
! (set_attr "atype" "*,agen")
(set_attr "length" "*,14")])
; Compare a block of arbitrary length.
***************
*** 1931,1937 ****
"TARGET_64BIT"
"clcl\\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "atype" "mem")
(set_attr "type" "vs")])
(define_insn "cmpstr_long_31"
--- 1955,1960 ----
***************
*** 1945,1951 ****
"!TARGET_64BIT"
"clcl\\t%0,%1"
[(set_attr "op_type" "RR")
- (set_attr "atype" "mem")
(set_attr "type" "vs")])
; Convert condition code to integer in range (-1, 0, 1)
--- 1968,1973 ----
***************
*** 1964,1970 ****
}"
[(set_attr "op_type" "NN")
(set_attr "length" "16")
- (set_attr "atype" "reg")
(set_attr "type" "other")])
(define_insn "cmpint_di"
--- 1986,1991 ----
***************
*** 1981,1987 ****
}"
[(set_attr "op_type" "NN")
(set_attr "length" "22")
- (set_attr "atype" "reg")
(set_attr "type" "other")])
--- 2002,2007 ----
***************
*** 1995,2002 ****
(clobber (reg:CC 33))]
""
"icm\\t%0,8,%1"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn "*sethighhisi"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 2015,2021 ----
(clobber (reg:CC 33))]
""
"icm\\t%0,8,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*sethighhisi"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 2004,2011 ****
(clobber (reg:CC 33))]
""
"icm\\t%0,12,%1"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 2023,2029 ----
(clobber (reg:CC 33))]
""
"icm\\t%0,12,%1"
! [(set_attr "op_type" "RS")])
(define_insn "*sethighqidi_64"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 2013,2020 ****
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "mem")])
(define_insn "*sethighqidi_31"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 2031,2037 ----
(clobber (reg:CC 33))]
"TARGET_64BIT"
"icmh\\t%0,8,%1"
! [(set_attr "op_type" "RSE")])
(define_insn "*sethighqidi_31"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 2022,2029 ****
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"icm\\t%0,8,%1"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "mem")])
(define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 2039,2045 ----
(clobber (reg:CC 33))]
"!TARGET_64BIT"
"icm\\t%0,8,%1"
! [(set_attr "op_type" "RS")])
(define_insn_and_split "*extractqi"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 2045,2051 ****
operands[1] = change_address (operands[1], QImode, 0);
}"
[(set_attr "type" "o2")
! (set_attr "atype" "mem")])
(define_insn_and_split "*extracthi"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 2061,2067 ----
operands[1] = change_address (operands[1], QImode, 0);
}"
[(set_attr "type" "o2")
! (set_attr "atype" "agen")])
(define_insn_and_split "*extracthi"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 2067,2073 ****
operands[1] = change_address (operands[1], HImode, 0);
}"
[(set_attr "type" "o2")
! (set_attr "atype" "mem")])
;
; extendsidi2 instruction pattern(s).
--- 2083,2089 ----
operands[1] = change_address (operands[1], HImode, 0);
}"
[(set_attr "type" "o2")
! (set_attr "atype" "agen")])
;
; extendsidi2 instruction pattern(s).
***************
*** 2097,2104 ****
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
;
; extendhidi2 instruction pattern(s).
--- 2113,2119 ----
"@
lgfr\\t%0,%1
lgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
;
; extendhidi2 instruction pattern(s).
***************
*** 2132,2139 ****
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
! [(set_attr "op_type" "RXE")
! (set_attr "atype" "mem")])
;
; extendqidi2 instruction pattern(s).
--- 2147,2153 ----
(sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"lgh\\t%0,%1"
! [(set_attr "op_type" "RXE")])
;
; extendqidi2 instruction pattern(s).
***************
*** 2196,2203 ****
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
""
"lh\\t%0,%1"
! [(set_attr "op_type" "RX")
! (set_attr "atype" "mem")])
;
; extendqisi2 instruction pattern(s).
--- 2210,2216 ----
(sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
""
"lh\\t%0,%1"
! [(set_attr "op_type" "RX")])
;
; extendqisi2 instruction pattern(s).
***************
*** 2260,2267 ****
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
;
; zero_extendhidi2 instruction pattern(s).
--- 2273,2279 ----
"@
llgfr\\t%0,%1
llgf\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
;
; zero_extendhidi2 instruction pattern(s).
***************
*** 2295,2302 ****
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXE")
! (set_attr "atype" "mem")])
;
; zero_extendqidi2 instruction pattern(s)
--- 2307,2313 ----
(zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXE")])
;
; zero_extendqidi2 instruction pattern(s)
***************
*** 2330,2337 ****
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")
! (set_attr "atype" "mem")])
;
; zero_extendhisi2 instruction pattern(s).
--- 2341,2347 ----
(zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")])
;
; zero_extendhisi2 instruction pattern(s).
***************
*** 2354,2361 ****
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXE")
! (set_attr "atype" "mem")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
--- 2364,2370 ----
(zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgh\\t%0,%1"
! [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendhisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
***************
*** 2370,2376 ****
(clobber (reg:CC 33))])]
"operands[2] = gen_lowpart (HImode, operands[0]);"
[(set_attr "type" "o2")
! (set_attr "atype" "mem")])
;
; zero_extendqisi2 instruction pattern(s).
--- 2379,2385 ----
(clobber (reg:CC 33))])]
"operands[2] = gen_lowpart (HImode, operands[0]);"
[(set_attr "type" "o2")
! (set_attr "atype" "agen")])
;
; zero_extendqisi2 instruction pattern(s).
***************
*** 2393,2400 ****
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")
! (set_attr "atype" "mem")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
--- 2402,2408 ----
(zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendqisi2_31"
[(set (match_operand:SI 0 "register_operand" "=&d")
***************
*** 2406,2412 ****
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "type" "o2")
! (set_attr "atype" "mem")])
;
; zero_extendqihi2 instruction pattern(s).
--- 2414,2420 ----
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "type" "o2")
! (set_attr "atype" "agen")])
;
; zero_extendqihi2 instruction pattern(s).
***************
*** 2429,2436 ****
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")
! (set_attr "atype" "mem")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
--- 2437,2443 ----
(zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
"TARGET_64BIT"
"llgc\\t%0,%1"
! [(set_attr "op_type" "RXE")])
(define_insn_and_split "*zero_extendqihi2_31"
[(set (match_operand:HI 0 "register_operand" "=&d")
***************
*** 2442,2448 ****
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "type" "o2")
! (set_attr "atype" "mem")])
;
--- 2449,2455 ----
(set (strict_low_part (match_dup 2)) (match_dup 1))]
"operands[2] = gen_lowpart (QImode, operands[0]);"
[(set_attr "type" "o2")
! (set_attr "atype" "agen")])
;
***************
*** 2495,2501 ****
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgdbr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "other")])
;
; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
--- 2502,2508 ----
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgdbr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "ftoi")])
;
; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
***************
*** 2582,2588 ****
return \"l\\t%0,%N4\";
}"
[(set_attr "op_type" "NN")
! (set_attr "type" "other")
(set_attr "length" "20")])
;
--- 2589,2596 ----
return \"l\\t%0,%N4\";
}"
[(set_attr "op_type" "NN")
! (set_attr "type" "ftoi")
! (set_attr "atype" "agen")
(set_attr "length" "20")])
;
***************
*** 2636,2642 ****
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "other")])
;
; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
--- 2644,2650 ----
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cgebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "ftoi")])
;
; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
***************
*** 2699,2705 ****
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cfebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "other")])
;
; floatdidf2 instruction pattern(s).
--- 2707,2713 ----
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cfebr\\t%0,%h2,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "ftoi")])
;
; floatdidf2 instruction pattern(s).
***************
*** 2725,2731 ****
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cegbr\\t%0,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "other" )])
;
; floatsidf2 instruction pattern(s).
--- 2733,2739 ----
"TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cegbr\\t%0,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "itof" )])
;
; floatsidf2 instruction pattern(s).
***************
*** 2758,2764 ****
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdfbr\\t%0,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "other" )])
(define_insn "floatsidf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
--- 2766,2772 ----
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cdfbr\\t%0,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "itof" )])
(define_insn "floatsidf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
***************
*** 2777,2782 ****
--- 2785,2791 ----
}"
[(set_attr "op_type" "NN")
(set_attr "type" "other" )
+ (set_attr "atype" "agen")
(set_attr "length" "20")])
;
***************
*** 2808,2814 ****
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cefbr\\t%0,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "other" )])
;
; truncdfsf2 instruction pattern(s).
--- 2817,2823 ----
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"cefbr\\t%0,%1"
[(set_attr "op_type" "RRE")
! (set_attr "type" "itof" )])
;
; truncdfsf2 instruction pattern(s).
***************
*** 2835,2841 ****
lrer\\t%0,%1
le\\t%0,%1"
[(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
;
; extendsfdf2 instruction pattern(s).
--- 2844,2850 ----
lrer\\t%0,%1
le\\t%0,%1"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "floads,floads")])
;
; extendsfdf2 instruction pattern(s).
***************
*** 2861,2867 ****
"@
ldebr\\t%0,%1
ldeb\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
--- 2870,2877 ----
"@
ldebr\\t%0,%1
ldeb\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "floads,floads")])
(define_insn "extendsfdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
***************
*** 2871,2878 ****
"@
sdr\\t%0,%0\;ler\\t%0,%1
sdr\\t%0,%0\;le\\t%0,%1"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")
(set_attr "type" "o2,o2")])
--- 2881,2889 ----
"@
sdr\\t%0,%0\;ler\\t%0,%1
sdr\\t%0,%0\;le\\t%0,%1"
! [(set_attr "op_type" "NN,NN")
! (set_attr "atype" "reg,agen")
! (set_attr "length" "4,6")
(set_attr "type" "o2,o2")])
***************
*** 2899,2905 ****
&& preferred_la_operand_p (operands[1], 1)"
"#"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_split
--- 2910,2915 ----
***************
*** 2919,2926 ****
"@
agfr\\t%0,%2
agf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddi3_zero_cc"
[(set (reg 33)
--- 2929,2935 ----
"@
agfr\\t%0,%2
agf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero_cc"
[(set (reg 33)
***************
*** 2933,2940 ****
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddi3_zero_cconly"
[(set (reg 33)
--- 2942,2948 ----
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero_cconly"
[(set (reg 33)
***************
*** 2946,2953 ****
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 2954,2960 ----
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 2958,2965 ****
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddi3_imm_cc"
[(set (reg 33)
--- 2965,2971 ----
"@
algfr\\t%0,%2
algf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_imm_cc"
[(set (reg 33)
***************
*** 2972,2979 ****
&& s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"aghi\\t%0,%h2"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "*adddi3_cc"
[(set (reg 33)
--- 2978,2984 ----
&& s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"aghi\\t%0,%h2"
! [(set_attr "op_type" "RI")])
(define_insn "*adddi3_cc"
[(set (reg 33)
***************
*** 2986,2993 ****
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddi3_cconly"
[(set (reg 33)
--- 2991,2997 ----
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_cconly"
[(set (reg 33)
***************
*** 2999,3006 ****
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddi3_cconly2"
[(set (reg 33)
--- 3003,3009 ----
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_cconly2"
[(set (reg 33)
***************
*** 3011,3018 ****
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
--- 3014,3020 ----
"@
algr\\t%0,%2
alg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*adddi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d,d")
***************
*** 3024,3031 ****
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RXE")
! (set_attr "atype" "reg,reg,mem")])
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
--- 3026,3032 ----
agr\\t%0,%2
aghi\\t%0,%h2
ag\\t%0,%2"
! [(set_attr "op_type" "RRE,RI,RXE")])
(define_insn_and_split "*adddi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
***************
*** 3076,3082 ****
"TARGET_64BIT"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_expand "reload_indi"
--- 3077,3082 ----
***************
*** 3103,3109 ****
&& preferred_la_operand_p (operands[1], 1)"
"#"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_split
--- 3103,3108 ----
***************
*** 3124,3131 ****
"s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"ahi\\t%0,%h2"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "*addsi3_carry1_cc"
[(set (reg 33)
--- 3123,3129 ----
"s390_match_ccmode (insn, CCAmode)
&& CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')"
"ahi\\t%0,%h2"
! [(set_attr "op_type" "RI")])
(define_insn "*addsi3_carry1_cc"
[(set (reg 33)
***************
*** 3138,3145 ****
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg 33)
--- 3136,3142 ----
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry1_cconly"
[(set (reg 33)
***************
*** 3151,3158 ****
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsi3_carry2_cc"
[(set (reg 33)
--- 3148,3154 ----
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry2_cc"
[(set (reg 33)
***************
*** 3165,3172 ****
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg 33)
--- 3161,3167 ----
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_carry2_cconly"
[(set (reg 33)
***************
*** 3178,3185 ****
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsi3_cc"
[(set (reg 33)
--- 3173,3179 ----
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cc"
[(set (reg 33)
***************
*** 3192,3199 ****
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsi3_cconly"
[(set (reg 33)
--- 3186,3192 ----
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cconly"
[(set (reg 33)
***************
*** 3205,3212 ****
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsi3_cconly2"
[(set (reg 33)
--- 3198,3204 ----
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_cconly2"
[(set (reg 33)
***************
*** 3217,3224 ****
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 3209,3215 ----
"@
alr\\t%0,%2
al\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*addsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 3227,3234 ****
(clobber (reg:CC 33))]
""
"ah\\t%0,%2"
! [(set_attr "op_type" "RX")
! (set_attr "atype" "mem")])
(define_insn "*addsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 3218,3224 ----
(clobber (reg:CC 33))]
""
"ah\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "*addsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 3237,3244 ****
(clobber (reg:CC 33))]
""
"ah\\t%0,%2"
! [(set_attr "op_type" "RX")
! (set_attr "atype" "mem")])
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
--- 3227,3233 ----
(clobber (reg:CC 33))]
""
"ah\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d,d")
***************
*** 3250,3257 ****
ar\\t%0,%2
ahi\\t%0,%h2
a\\t%0,%2"
! [(set_attr "op_type" "RR,RI,RX")
! (set_attr "atype" "reg,reg,mem")])
(define_insn "*la_31"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 3239,3245 ----
ar\\t%0,%2
ahi\\t%0,%h2
a\\t%0,%2"
! [(set_attr "op_type" "RR,RI,RX")])
(define_insn "*la_31"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 3259,3265 ****
"!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_insn "*la_31_and"
--- 3247,3252 ----
***************
*** 3269,3275 ****
"!TARGET_64BIT"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_insn_and_split "*la_31_and_cc"
--- 3256,3261 ----
***************
*** 3284,3290 ****
(and:SI (match_dup 1) (const_int 2147483647)))]
""
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_insn "force_la_31"
--- 3270,3275 ----
***************
*** 3294,3300 ****
"!TARGET_64BIT"
"la\\t%0,%a1"
[(set_attr "op_type" "RX")
- (set_attr "atype" "mem")
(set_attr "type" "la")])
(define_expand "reload_insi"
--- 3279,3284 ----
***************
*** 3332,3338 ****
adbr\\t%0,%2
adb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
--- 3316,3322 ----
adbr\\t%0,%2
adb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fsimpd,fsimpd")])
(define_insn "*adddf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
***************
*** 3344,3350 ****
adr\\t%0,%2
ad\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
;
; addsf3 instruction pattern(s).
--- 3328,3334 ----
adr\\t%0,%2
ad\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fsimpd,fsimpd")])
;
; addsf3 instruction pattern(s).
***************
*** 3369,3375 ****
aebr\\t%0,%2
aeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
--- 3353,3359 ----
aebr\\t%0,%2
aeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fsimps,fsimps")])
(define_insn "*addsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
***************
*** 3381,3387 ****
aer\\t%0,%2
ae\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
;;
--- 3365,3371 ----
aer\\t%0,%2
ae\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fsimps,fsimps")])
;;
***************
*** 3401,3408 ****
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subdi3_zero_cc"
[(set (reg 33)
--- 3385,3391 ----
"@
sgfr\\t%0,%2
sgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero_cc"
[(set (reg 33)
***************
*** 3415,3422 ****
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subdi3_zero_cconly"
[(set (reg 33)
--- 3398,3404 ----
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero_cconly"
[(set (reg 33)
***************
*** 3428,3435 ****
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 3410,3416 ----
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_zero"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 3440,3447 ****
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subdi3_cc"
[(set (reg 33)
--- 3421,3427 ----
"@
slgfr\\t%0,%2
slgf\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_cc"
[(set (reg 33)
***************
*** 3454,3461 ****
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subdi3_cconly"
[(set (reg 33)
--- 3434,3440 ----
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_cconly"
[(set (reg 33)
***************
*** 3467,3474 ****
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 3446,3452 ----
"@
slgr\\t%0,%2
slg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*subdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 3479,3486 ****
"@
sgr\\t%0,%2
sg\\t%0,%2"
! [(set_attr "op_type" "RRE,RRE")
! (set_attr "atype" "reg,mem")])
(define_insn_and_split "*subdi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
--- 3457,3463 ----
"@
sgr\\t%0,%2
sg\\t%0,%2"
! [(set_attr "op_type" "RRE,RRE")])
(define_insn_and_split "*subdi3_31"
[(set (match_operand:DI 0 "register_operand" "=&d")
***************
*** 3540,3547 ****
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*subsi3_borrow_cconly"
[(set (reg 33)
--- 3517,3523 ----
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_borrow_cconly"
[(set (reg 33)
***************
*** 3553,3560 ****
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*subsi3_cc"
[(set (reg 33)
--- 3529,3535 ----
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_cc"
[(set (reg 33)
***************
*** 3567,3574 ****
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*subsi3_cconly"
[(set (reg 33)
--- 3542,3548 ----
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_cconly"
[(set (reg 33)
***************
*** 3580,3587 ****
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*subsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 3554,3560 ----
"@
slr\\t%0,%2
sl\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*subsi3_sign"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 3590,3597 ****
(clobber (reg:CC 33))]
""
"sh\\t%0,%2"
! [(set_attr "op_type" "RX")
! (set_attr "atype" "mem")])
(define_insn "*subsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 3563,3569 ----
(clobber (reg:CC 33))]
""
"sh\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "*subsi3_sub"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 3600,3607 ****
(clobber (reg:CC 33))]
""
"sh\\t%0,%2"
! [(set_attr "op_type" "RX")
! (set_attr "atype" "mem")])
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
--- 3572,3578 ----
(clobber (reg:CC 33))]
""
"sh\\t%0,%2"
! [(set_attr "op_type" "RX")])
(define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
***************
*** 3612,3619 ****
"@
sr\\t%0,%2
s\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
;
--- 3583,3589 ----
"@
sr\\t%0,%2
s\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
;
***************
*** 3639,3645 ****
sdbr\\t%0,%2
sdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
--- 3609,3615 ----
sdbr\\t%0,%2
sdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fsimpd,fsimpd")])
(define_insn "*subdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
***************
*** 3651,3657 ****
sdr\\t%0,%2
sd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
;
; subsf3 instruction pattern(s).
--- 3621,3627 ----
sdr\\t%0,%2
sd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fsimpd,fsimpd")])
;
; subsf3 instruction pattern(s).
***************
*** 3676,3682 ****
sebr\\t%0,%2
seb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
--- 3646,3652 ----
sebr\\t%0,%2
seb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fsimps,fsimps")])
(define_insn "*subsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
***************
*** 3688,3694 ****
ser\\t%0,%2
se\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
;;
--- 3658,3664 ----
ser\\t%0,%2
se\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fsimps,fsimps")])
;;
***************
*** 3708,3714 ****
msgfr\\t%0,%2
msgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
- (set_attr "atype" "reg,mem")
(set_attr "type" "imul")])
--- 3678,3683 ----
***************
*** 3722,3728 ****
mghi\\t%0,%h2
msg\\t%0,%2"
[(set_attr "op_type" "RRE,RI,RXE")
- (set_attr "atype" "reg,reg,mem")
(set_attr "type" "imul")])
;
--- 3691,3696 ----
***************
*** 3739,3745 ****
mhi\\t%0,%h2
ms\\t%0,%2"
[(set_attr "op_type" "RRE,RI,RX")
- (set_attr "atype" "reg,reg,mem")
(set_attr "type" "imul")])
;
--- 3707,3712 ----
***************
*** 3778,3784 ****
mr\\t%0,%2
m\\t%0,%2"
[(set_attr "op_type" "RR,RX")
- (set_attr "atype" "reg,mem")
(set_attr "type" "imul")])
;
--- 3745,3750 ----
***************
*** 3804,3811 ****
mdbr\\t%0,%2
mdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fmul")
! (set_attr "atype" "reg,mem")])
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
--- 3770,3776 ----
mdbr\\t%0,%2
mdb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fmuld")])
(define_insn "*muldf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
***************
*** 3817,3824 ****
mdr\\t%0,%2
md\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fmul")
! (set_attr "atype" "reg,mem")])
;
; mulsf3 instruction pattern(s).
--- 3782,3788 ----
mdr\\t%0,%2
md\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fmuld")])
;
; mulsf3 instruction pattern(s).
***************
*** 3843,3850 ****
meebr\\t%0,%2
meeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fmul")
! (set_attr "atype" "reg,mem")])
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
--- 3807,3813 ----
meebr\\t%0,%2
meeb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fmuls")])
(define_insn "*mulsf3_ibm"
[(set (match_operand:SF 0 "register_operand" "=f,f")
***************
*** 3856,3863 ****
mer\\t%0,%2
me\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fmul")
! (set_attr "atype" "reg,mem")])
;;
--- 3819,3825 ----
mer\\t%0,%2
me\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fmuls")])
;;
***************
*** 3923,3930 ****
dsgr\\t%0,%2
dsg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "idiv")
! (set_attr "atype" "reg,mem")])
(define_insn "divmodtisi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
--- 3885,3891 ----
dsgr\\t%0,%2
dsg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "idiv")])
(define_insn "divmodtisi3"
[(set (match_operand:TI 0 "register_operand" "=d,d")
***************
*** 3942,3949 ****
dsgfr\\t%0,%2
dsgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "idiv")
! (set_attr "atype" "reg,mem")])
;
; udivmoddi4 instruction pattern(s).
--- 3903,3909 ----
dsgfr\\t%0,%2
dsgf\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "idiv")])
;
; udivmoddi4 instruction pattern(s).
***************
*** 4005,4012 ****
dlgr\\t%0,%2
dlg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "idiv")
! (set_attr "atype" "reg,mem")])
;
; divmodsi4 instruction pattern(s).
--- 3965,3971 ----
dlgr\\t%0,%2
dlg\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "idiv")])
;
; divmodsi4 instruction pattern(s).
***************
*** 4066,4073 ****
dr\\t%0,%2
d\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "idiv")
! (set_attr "atype" "reg,mem")])
;
; udivsi3 and umodsi3 instruction pattern(s).
--- 4025,4031 ----
dr\\t%0,%2
d\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "idiv")])
;
; udivsi3 and umodsi3 instruction pattern(s).
***************
*** 4281,4288 ****
ddbr\\t%0,%2
ddb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fdiv")
! (set_attr "atype" "reg,mem")])
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
--- 4239,4245 ----
ddbr\\t%0,%2
ddb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fdivd")])
(define_insn "*divdf3_ibm"
[(set (match_operand:DF 0 "register_operand" "=f,f")
***************
*** 4294,4301 ****
ddr\\t%0,%2
dd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fdiv")
! (set_attr "atype" "reg,mem")])
;
; divsf3 instruction pattern(s).
--- 4251,4257 ----
ddr\\t%0,%2
dd\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fdivd")])
;
; divsf3 instruction pattern(s).
***************
*** 4320,4327 ****
debr\\t%0,%2
deb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fdiv")
! (set_attr "atype" "reg,mem")])
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
--- 4276,4282 ----
debr\\t%0,%2
deb\\t%0,%2"
[(set_attr "op_type" "RRE,RXE")
! (set_attr "type" "fdivs")])
(define_insn "*divsf3"
[(set (match_operand:SF 0 "register_operand" "=f,f")
***************
*** 4333,4340 ****
der\\t%0,%2
de\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fdiv")
! (set_attr "atype" "reg,mem")])
;;
--- 4288,4294 ----
der\\t%0,%2
de\\t%0,%2"
[(set_attr "op_type" "RR,RX")
! (set_attr "type" "fdivs")])
;;
***************
*** 4356,4363 ****
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*anddi3_cconly"
[(set (reg 33)
--- 4310,4316 ----
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_cconly"
[(set (reg 33)
***************
*** 4369,4376 ****
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 4322,4328 ----
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_ni"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 4392,4399 ****
default: abort ();
}
}"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "anddi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 4344,4350 ----
default: abort ();
}
}"
! [(set_attr "op_type" "RI")])
(define_insn "anddi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 4404,4411 ****
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4355,4361 ----
"@
ngr\\t%0,%2
ng\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*anddi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4414,4421 ****
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*anddi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4364,4370 ----
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*anddi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4424,4431 ****
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; andsi3 instruction pattern(s).
--- 4373,4379 ----
(clobber (reg:CC 33))]
""
"nc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; andsi3 instruction pattern(s).
***************
*** 4442,4449 ****
"@
nr\\t%0,%2
n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*andsi3_cconly"
[(set (reg 33)
--- 4390,4396 ----
"@
nr\\t%0,%2
n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_cconly"
[(set (reg 33)
***************
*** 4455,4462 ****
"@
nr\\t%0,%2
n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 4402,4408 ----
"@
nr\\t%0,%2
n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_ni"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 4476,4483 ****
default: abort ();
}
}"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
--- 4422,4428 ----
default: abort ();
}
}"
! [(set_attr "op_type" "RI")])
(define_insn "andsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
***************
*** 4488,4495 ****
"@
nr\\t%0,%2
n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4433,4439 ----
"@
nr\\t%0,%2
n\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*andsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4498,4505 ****
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*andsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4442,4448 ----
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*andsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4508,4515 ****
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; andhi3 instruction pattern(s).
--- 4451,4457 ----
(clobber (reg:CC 33))]
""
"nc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; andhi3 instruction pattern(s).
***************
*** 4524,4531 ****
"@
nr\\t%0,%2
nill\\t%0,%x2"
! [(set_attr "op_type" "RR,RI")
! (set_attr "atype" "reg")])
(define_insn "andhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
--- 4466,4472 ----
"@
nr\\t%0,%2
nill\\t%0,%x2"
! [(set_attr "op_type" "RR,RI")])
(define_insn "andhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
***************
*** 4534,4541 ****
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
! [(set_attr "op_type" "RR")
! (set_attr "atype" "reg")])
(define_insn "*andhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
--- 4475,4481 ----
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
! [(set_attr "op_type" "RR")])
(define_insn "*andhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
***************
*** 4544,4551 ****
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*andhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
--- 4484,4490 ----
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*andhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
***************
*** 4554,4561 ****
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; andqi3 instruction pattern(s).
--- 4493,4499 ----
(clobber (reg:CC 33))]
""
"nc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; andqi3 instruction pattern(s).
***************
*** 4570,4577 ****
"@
nr\\t%0,%2
nill\\t%0,%b2"
! [(set_attr "op_type" "RR,RI")
! (set_attr "atype" "reg")])
(define_insn "andqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
--- 4508,4514 ----
"@
nr\\t%0,%2
nill\\t%0,%b2"
! [(set_attr "op_type" "RR,RI")])
(define_insn "andqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
***************
*** 4580,4587 ****
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
! [(set_attr "op_type" "RR")
! (set_attr "atype" "reg")])
(define_insn "*andqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
--- 4517,4523 ----
(clobber (reg:CC 33))]
""
"nr\\t%0,%2"
! [(set_attr "op_type" "RR")])
(define_insn "*andqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
***************
*** 4592,4599 ****
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")
! (set_attr "atype" "mem")])
(define_insn "*andqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
--- 4528,4534 ----
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
(define_insn "*andqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
***************
*** 4604,4611 ****
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")
! (set_attr "atype" "mem")])
;;
--- 4539,4545 ----
"@
ni\\t%0,%b1
nc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
;;
***************
*** 4627,4634 ****
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*iordi3_cconly"
[(set (reg 33)
--- 4561,4567 ----
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_cconly"
[(set (reg 33)
***************
*** 4640,4647 ****
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 4573,4579 ----
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_oi"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 4663,4670 ****
default: abort ();
}
}"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "iordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 4595,4601 ----
default: abort ();
}
}"
! [(set_attr "op_type" "RI")])
(define_insn "iordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 4675,4682 ****
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4606,4612 ----
"@
ogr\\t%0,%2
og\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*iordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4685,4692 ****
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*iordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4615,4621 ----
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*iordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4695,4702 ****
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; iorsi3 instruction pattern(s).
--- 4624,4630 ----
(clobber (reg:CC 33))]
""
"oc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; iorsi3 instruction pattern(s).
***************
*** 4713,4720 ****
"@
or\\t%0,%2
o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*iorsi3_cconly"
[(set (reg 33)
--- 4641,4647 ----
"@
or\\t%0,%2
o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_cconly"
[(set (reg 33)
***************
*** 4726,4733 ****
"@
or\\t%0,%2
o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d")
--- 4653,4659 ----
"@
or\\t%0,%2
o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_oi"
[(set (match_operand:SI 0 "register_operand" "=d")
***************
*** 4747,4754 ****
default: abort ();
}
}"
! [(set_attr "op_type" "RI")
! (set_attr "atype" "reg")])
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
--- 4673,4679 ----
default: abort ();
}
}"
! [(set_attr "op_type" "RI")])
(define_insn "iorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
***************
*** 4759,4766 ****
"@
or\\t%0,%2
o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4684,4690 ----
"@
or\\t%0,%2
o\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*iorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4769,4776 ****
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*iorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4693,4699 ----
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*iorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4779,4786 ****
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; iorhi3 instruction pattern(s).
--- 4702,4708 ----
(clobber (reg:CC 33))]
""
"oc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; iorhi3 instruction pattern(s).
***************
*** 4795,4802 ****
"@
or\\t%0,%2
oill\\t%0,%x2"
! [(set_attr "op_type" "RR,RI")
! (set_attr "atype" "reg")])
(define_insn "iorhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
--- 4717,4723 ----
"@
or\\t%0,%2
oill\\t%0,%x2"
! [(set_attr "op_type" "RR,RI")])
(define_insn "iorhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
***************
*** 4805,4812 ****
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
! [(set_attr "op_type" "RR")
! (set_attr "atype" "reg")])
(define_insn "*iorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
--- 4726,4732 ----
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
! [(set_attr "op_type" "RR")])
(define_insn "*iorhi3_ss"
[(set (match_operand:HI 0 "s_operand" "=Q")
***************
*** 4815,4822 ****
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*iorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
--- 4735,4741 ----
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*iorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
***************
*** 4825,4832 ****
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; iorqi3 instruction pattern(s).
--- 4744,4750 ----
(clobber (reg:CC 33))]
""
"oc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; iorqi3 instruction pattern(s).
***************
*** 4841,4848 ****
"@
or\\t%0,%2
oill\\t%0,%b2"
! [(set_attr "op_type" "RR,RI")
! (set_attr "atype" "reg")])
(define_insn "iorqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
--- 4759,4765 ----
"@
or\\t%0,%2
oill\\t%0,%b2"
! [(set_attr "op_type" "RR,RI")])
(define_insn "iorqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
***************
*** 4851,4858 ****
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
! [(set_attr "op_type" "RR")
! (set_attr "atype" "reg")])
(define_insn "*iorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
--- 4768,4774 ----
(clobber (reg:CC 33))]
""
"or\\t%0,%2"
! [(set_attr "op_type" "RR")])
(define_insn "*iorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
***************
*** 4863,4870 ****
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")
! (set_attr "atype" "reg,mem")])
(define_insn "*iorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
--- 4779,4785 ----
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
(define_insn "*iorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
***************
*** 4875,4882 ****
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")
! (set_attr "atype" "reg,mem")])
;;
--- 4790,4796 ----
"@
oi\\t%0,%b1
oc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
;;
***************
*** 4898,4905 ****
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*xordi3_cconly"
[(set (reg 33)
--- 4812,4818 ----
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*xordi3_cconly"
[(set (reg 33)
***************
*** 4911,4918 ****
"@
xgr\\t%0,%2
xr\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 4824,4830 ----
"@
xgr\\t%0,%2
xr\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "xordi3"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 4923,4930 ****
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")
! (set_attr "atype" "reg,mem")])
(define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4835,4841 ----
"@
xgr\\t%0,%2
xg\\t%0,%2"
! [(set_attr "op_type" "RRE,RXE")])
(define_insn "*xordi3_ss"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4933,4940 ****
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*xordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
--- 4844,4850 ----
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*xordi3_ss_inv"
[(set (match_operand:DI 0 "s_operand" "=Q")
***************
*** 4943,4950 ****
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; xorsi3 instruction pattern(s).
--- 4853,4859 ----
(clobber (reg:CC 33))]
""
"xc\\t%O0(8,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; xorsi3 instruction pattern(s).
***************
*** 4961,4968 ****
"@
xr\\t%0,%2
x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*xorsi3_cconly"
[(set (reg 33)
--- 4870,4876 ----
"@
xr\\t%0,%2
x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*xorsi3_cconly"
[(set (reg 33)
***************
*** 4974,4981 ****
"@
xr\\t%0,%2
x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
--- 4882,4888 ----
"@
xr\\t%0,%2
x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "xorsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
***************
*** 4986,4993 ****
"@
xr\\t%0,%2
x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")
! (set_attr "atype" "reg,mem")])
(define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4893,4899 ----
"@
xr\\t%0,%2
x\\t%0,%2"
! [(set_attr "op_type" "RR,RX")])
(define_insn "*xorsi3_ss"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 4996,5003 ****
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*xorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
--- 4902,4908 ----
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*xorsi3_ss_inv"
[(set (match_operand:SI 0 "s_operand" "=Q")
***************
*** 5006,5013 ****
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; xorhi3 instruction pattern(s).
--- 4911,4917 ----
(clobber (reg:CC 33))]
""
"xc\\t%O0(4,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; xorhi3 instruction pattern(s).
***************
*** 5030,5037 ****
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
(define_insn "*xorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
--- 4934,4940 ----
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")])
(define_insn "*xorhi3_ss_inv"
[(set (match_operand:HI 0 "s_operand" "=Q")
***************
*** 5040,5047 ****
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")
! (set_attr "atype" "mem")])
;
; xorqi3 instruction pattern(s).
--- 4943,4949 ----
(clobber (reg:CC 33))]
""
"xc\\t%O0(2,%R0),%1"
! [(set_attr "op_type" "SS")])
;
; xorqi3 instruction pattern(s).
***************
*** 5054,5061 ****
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
! [(set_attr "op_type" "RR")
! (set_attr "atype" "reg")])
(define_insn "*xorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
--- 4956,4962 ----
(clobber (reg:CC 33))]
""
"xr\\t%0,%2"
! [(set_attr "op_type" "RR")])
(define_insn "*xorqi3_ss"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
***************
*** 5066,5073 ****
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")
! (set_attr "atype" "mem")])
(define_insn "*xorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
--- 4967,4973 ----
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
(define_insn "*xorqi3_ss_inv"
[(set (match_operand:QI 0 "s_operand" "=Q,Q")
***************
*** 5078,5085 ****
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")
! (set_attr "atype" "mem")])
;;
--- 4978,4984 ----
"@
xi\\t%0,%b1
xc\\t%O0(1,%R0),%1"
! [(set_attr "op_type" "SI,SS")])
;;
***************
*** 5157,5163 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\\t%0,%1"
! [(set_attr "op_type" "RRE")])
(define_insn "*negdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
--- 5056,5063 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcdbr\\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "type" "fsimpd")])
(define_insn "*negdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
***************
*** 5165,5171 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcdr\\t%0,%1"
! [(set_attr "op_type" "RR")])
;
; negsf2 instruction pattern(s).
--- 5065,5072 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcdr\\t%0,%1"
! [(set_attr "op_type" "RR")
! (set_attr "type" "fsimpd")])
;
; negsf2 instruction pattern(s).
***************
*** 5185,5191 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\\t%0,%1"
! [(set_attr "op_type" "RRE")])
(define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
--- 5086,5093 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lcebr\\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "type" "fsimps")])
(define_insn "*negsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
***************
*** 5193,5199 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcer\\t%0,%1"
! [(set_attr "op_type" "RR")])
;;
--- 5095,5102 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lcer\\t%0,%1"
! [(set_attr "op_type" "RR")
! (set_attr "type" "fsimps")])
;;
***************
*** 5242,5248 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\\t%0,%1"
! [(set_attr "op_type" "RRE")])
(define_insn "*absdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
--- 5145,5152 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpdbr\\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "type" "fsimpd")])
(define_insn "*absdf2_ibm"
[(set (match_operand:DF 0 "register_operand" "=f")
***************
*** 5250,5256 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lpdr\\t%0,%1"
! [(set_attr "op_type" "RR")])
;
; abssf2 instruction pattern(s).
--- 5154,5161 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lpdr\\t%0,%1"
! [(set_attr "op_type" "RR")
! (set_attr "type" "fsimpd")])
;
; abssf2 instruction pattern(s).
***************
*** 5270,5276 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\\t%0,%1"
! [(set_attr "op_type" "RRE")])
(define_insn "*abssf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f")
--- 5175,5182 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
"lpebr\\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "type" "fsimps")])
(define_insn "*abssf2_ibm"
[(set (match_operand:SF 0 "register_operand" "=f")
***************
*** 5278,5284 ****
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lper\\t%0,%1"
! [(set_attr "op_type" "RR")])
;;
;;- Square root instructions.
--- 5184,5191 ----
(clobber (reg:CC 33))]
"TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
"lper\\t%0,%1"
! [(set_attr "op_type" "RR")
! (set_attr "type" "fsimps")])
;;
;;- Square root instructions.
***************
*** 5295,5301 ****
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
! [(set_attr "op_type" "RRE,RSE")])
;
; sqrtsf2 instruction pattern(s).
--- 5202,5209 ----
"@
sqdbr\\t%0,%1
sqdb\\t%0,%1"
! [(set_attr "op_type" "RRE,RSE")
! (set_attr "type" "fsqrtd")])
;
; sqrtsf2 instruction pattern(s).
***************
*** 5308,5314 ****
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
! [(set_attr "op_type" "RRE,RSE")])
;;
;;- One complement instructions.
--- 5216,5223 ----
"@
sqebr\\t%0,%1
sqeb\\t%0,%1"
! [(set_attr "op_type" "RRE,RSE")
! (set_attr "type" "fsqrts")])
;;
;;- One complement instructions.
***************
*** 5383,5389 ****
"@
rllg\\t%0,%1,%c2
rllg\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")])
;
; rotlsi3 instruction pattern(s).
--- 5292,5299 ----
"@
rllg\\t%0,%1,%c2
rllg\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
;
; rotlsi3 instruction pattern(s).
***************
*** 5397,5403 ****
"@
rll\\t%0,%1,%c2
rll\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")])
;;
--- 5307,5314 ----
"@
rll\\t%0,%1,%c2
rll\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
;;
***************
*** 5423,5429 ****
"@
sldl\\t%0,%c2
sldl\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
(define_insn "*ashldi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 5334,5341 ----
"@
sldl\\t%0,%c2
sldl\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
(define_insn "*ashldi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 5433,5439 ****
"@
sllg\\t%0,%1,%2
sllg\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")])
;
; ashrdi3 instruction pattern(s).
--- 5345,5352 ----
"@
sllg\\t%0,%1,%2
sllg\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
;
; ashrdi3 instruction pattern(s).
***************
*** 5459,5465 ****
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
(define_insn "*ashrdi3_cconly_31"
[(set (reg 33)
--- 5372,5379 ----
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_31"
[(set (reg 33)
***************
*** 5471,5477 ****
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
(define_insn "*ashrdi3_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 5385,5392 ----
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
(define_insn "*ashrdi3_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 5482,5489 ****
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
!
(define_insn "*ashrdi3_cc_64"
[(set (reg 33)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
--- 5397,5405 ----
"@
srda\\t%0,%c2
srda\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
(define_insn "*ashrdi3_cc_64"
[(set (reg 33)
(compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d")
***************
*** 5495,5501 ****
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")])
(define_insn "*ashrdi3_cconly_64"
[(set (reg 33)
--- 5411,5418 ----
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
(define_insn "*ashrdi3_cconly_64"
[(set (reg 33)
***************
*** 5507,5513 ****
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")])
(define_insn "*ashrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 5424,5431 ----
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
(define_insn "*ashrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 5518,5524 ****
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")])
;
; ashlsi3 instruction pattern(s).
--- 5436,5444 ----
"@
srag\\t%0,%1,%c2
srag\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE")
! (set_attr "atype" "reg")])
!
;
; ashlsi3 instruction pattern(s).
***************
*** 5532,5538 ****
"@
sll\\t%0,%c2
sll\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
;
; ashrsi3 instruction pattern(s).
--- 5452,5459 ----
"@
sll\\t%0,%c2
sll\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
;
; ashrsi3 instruction pattern(s).
***************
*** 5549,5555 ****
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
(define_insn "*ashrsi3_cconly"
[(set (reg 33)
--- 5470,5478 ----
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
!
(define_insn "*ashrsi3_cconly"
[(set (reg 33)
***************
*** 5561,5567 ****
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
--- 5484,5491 ----
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d,d")
***************
*** 5572,5578 ****
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
;;
--- 5496,5503 ----
"@
sra\\t%0,%c2
sra\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
;;
***************
*** 5598,5604 ****
"@
srdl\\t%0,%c2
srdl\\t%0,0(%2)"
! [(set_attr "op_type" "RS,RS")])
(define_insn "*lshrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 5523,5530 ----
"@
srdl\\t%0,%c2
srdl\\t%0,0(%2)"
! [(set_attr "op_type" "RS,RS")
! (set_attr "atype" "reg")])
(define_insn "*lshrdi3_64"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 5608,5614 ****
"@
srlg\\t%0,%1,%c2
srlg\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE,RSE")])
;
; lshrsi3 instruction pattern(s).
--- 5534,5541 ----
"@
srlg\\t%0,%1,%c2
srlg\\t%0,%1,0(%2)"
! [(set_attr "op_type" "RSE,RSE")
! (set_attr "atype" "reg")])
;
; lshrsi3 instruction pattern(s).
***************
*** 5622,5628 ****
"@
srl\\t%0,%c2
srl\\t%0,0(%2)"
! [(set_attr "op_type" "RS")])
;;
--- 5549,5556 ----
"@
srl\\t%0,%c2
srl\\t%0,0(%2)"
! [(set_attr "op_type" "RS")
! (set_attr "atype" "reg")])
;;
***************
*** 5813,5818 ****
--- 5741,5747 ----
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
***************
*** 5838,5844 ****
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "atype" "mem")])
;;
--- 5767,5774 ----
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "type" "branch")
! (set_attr "atype" "agen")])
;;
***************
*** 5862,5867 ****
--- 5792,5798 ----
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
***************
*** 5887,5893 ****
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "atype" "mem")])
;;
;;- Trap instructions.
--- 5818,5825 ----
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "type" "branch")
! (set_attr "atype" "agen")])
;;
;;- Trap instructions.
***************
*** 5897,5903 ****
[(trap_if (const_int 1) (const_int 0))]
""
"j\\t.+2"
! [(set_attr "op_type" "RX")])
(define_expand "conditional_trap"
[(set (match_dup 2) (match_dup 3))
--- 5829,5836 ----
[(trap_if (const_int 1) (const_int 0))]
""
"j\\t.+2"
! [(set_attr "op_type" "RX")
! (set_attr "type" "branch")])
(define_expand "conditional_trap"
[(set (match_dup 2) (match_dup 3))
***************
*** 5922,5928 ****
(const_int 0))]
""
"j%C0\\t.+2";
! [(set_attr "op_type" "RX")])
;;
;;- Loop instructions.
--- 5855,5862 ----
(const_int 0))]
""
"j%C0\\t.+2";
! [(set_attr "op_type" "RI")
! (set_attr "type" "branch")])
;;
;;- Loop instructions.
***************
*** 5971,5976 ****
--- 5905,5911 ----
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
***************
*** 6001,6007 ****
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "atype" "mem")])
(define_split
[(set (pc)
--- 5936,5943 ----
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "type" "branch")
! (set_attr "atype" "agen")])
(define_split
[(set (pc)
***************
*** 6049,6054 ****
--- 5985,5991 ----
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int
60000))
(const_int 4) (const_int 12)))])
***************
*** 6075,6081 ****
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RRE") (const_string "RXE")))
! (set_attr "atype" "mem")])
(define_split
[(set (pc)
--- 6012,6019 ----
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RRE") (const_string "RXE")))
! (set_attr "type" "branch")
! (set_attr "atype" "agen")])
(define_split
[(set (pc)
***************
*** 6122,6127 ****
--- 6060,6066 ----
abort ();
}"
[(set_attr "op_type" "RI")
+ (set_attr "type" "branch")
(set (attr "length")
(cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
(const_int 4)
***************
*** 6147,6153 ****
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "atype" "mem")])
;
; casesi instruction pattern(s).
--- 6086,6093 ----
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "type" "branch")
! (set_attr "atype" "agen")])
;
; casesi instruction pattern(s).
***************
*** 6167,6173 ****
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "atype" "mem")])
(define_expand "casesi"
[(match_operand:SI 0 "general_operand" "")
--- 6107,6114 ----
[(set (attr "op_type")
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
! (set_attr "type" "branch")
! (set_attr "atype" "agen")])
(define_expand "casesi"
[(match_operand:SI 0 "general_operand" "")
***************
*** 6346,6352 ****
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "mem")])
(define_insn "basr_31"
[(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
--- 6287,6293 ----
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "agen")])
(define_insn "basr_31"
[(call (mem:QI (match_operand:SI 0 "register_operand" "a"))
***************
*** 6356,6362 ****
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "mem")])
(define_insn "bas_64"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
--- 6297,6303 ----
"basr\\t%2,%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "agen")])
(define_insn "bas_64"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
***************
*** 6365,6372 ****
"TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")
! (set_attr "atype" "mem")])
(define_insn "bas_31"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
--- 6306,6312 ----
"TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")])
(define_insn "bas_31"
[(call (mem:QI (match_operand:QI 0 "address_operand" "p"))
***************
*** 6375,6382 ****
"!TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")
! (set_attr "atype" "mem")])
;
--- 6315,6321 ----
"!TARGET_64BIT"
"bas\\t%2,%a0"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")])
;
***************
*** 6471,6477 ****
"TARGET_64BIT"
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
! (set_attr "type" "jsr")])
(define_insn "basr_r_31"
[(set (match_operand 0 "register_operand" "=df")
--- 6410,6417 ----
"TARGET_64BIT"
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
! (set_attr "type" "jsr")
! (set_attr "atype" "agen")])
(define_insn "basr_r_31"
[(set (match_operand 0 "register_operand" "=df")
***************
*** 6482,6488 ****
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "mem")])
(define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df")
--- 6422,6428 ----
"basr\\t%3,%1"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "agen")])
(define_insn "bas_r_64"
[(set (match_operand 0 "register_operand" "=df")
***************
*** 6492,6499 ****
"TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")
! (set_attr "atype" "mem")])
(define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df")
--- 6432,6438 ----
"TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")])
(define_insn "bas_r_31"
[(set (match_operand 0 "register_operand" "=df")
***************
*** 6503,6510 ****
"!TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")
! (set_attr "atype" "mem")])
;;
--- 6442,6448 ----
"!TARGET_64BIT"
"bas\\t%3,%a1"
[(set_attr "op_type" "RX")
! (set_attr "type" "jsr")])
;;
***************
*** 6808,6814 ****
"TARGET_64BIT"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
! (set_attr "type" "la")])
(define_insn "reload_anchor"
[(set (match_operand:SI 0 "register_operand" "=a")
--- 6746,6752 ----
"TARGET_64BIT"
"larl\\t%0,%1"
[(set_attr "op_type" "RIL")
! (set_attr "type" "larl")])
(define_insn "reload_anchor"
[(set (match_operand:SI 0 "register_operand" "=a")
***************
*** 6817,6822 ****
--- 6755,6761 ----
"l\\t%0,0(%1)\;la\\t%0,0(%0,%1)"
[(set_attr "op_type" "NN")
(set_attr "type" "la")
+ (set_attr "atype" "agen")
(set_attr "length" "8")])
(define_insn "pool"
***************
*** 6857,6863 ****
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "mem")])
(define_insn "*return_di"
[(return)
--- 6796,6802 ----
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "agen")])
(define_insn "*return_di"
[(return)
***************
*** 6866,6872 ****
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "mem")])
(define_insn "literal_pool_31"
[(unspec_volatile [(const_int 0)] 300)
--- 6805,6811 ----
"br\\t%0"
[(set_attr "op_type" "RR")
(set_attr "type" "jsr")
! (set_attr "atype" "agen")])
(define_insn "literal_pool_31"
[(unspec_volatile [(const_int 0)] 300)
***************
*** 6883,6889 ****
return \"\";
}"
[(set_attr "op_type" "NN")
! (set_attr "type" "la")])
(define_insn "literal_pool_64"
[(unspec_volatile [(const_int 0)] 300)
--- 6822,6828 ----
return \"\";
}"
[(set_attr "op_type" "NN")
! (set_attr "type" "larl")])
(define_insn "literal_pool_64"
[(unspec_volatile [(const_int 0)] 300)
***************
*** 6900,6903 ****
return \"\";
}"
[(set_attr "op_type" "NN")
! (set_attr "type" "la")])
--- 6839,6842 ----
return \"\";
}"
[(set_attr "op_type" "NN")
! (set_attr "type" "larl")])
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