[patch] h8300.md: Add two new patterns.

Kazu Hirata kazu@cs.umass.edu
Wed Feb 19 17:48:00 GMT 2003


Hi,

Attached is a patch to add two new patterns.

Both patterns often occur when -mint32 is used.

Tested on h8300 port.  Committed.

Kazu Hirata

2003-02-19  Kazu Hirata  <kazu@cs.umass.edu>

	* config/h8300/h8300.md (*iorsi3_two_qi_sext): New.
	(*ashiftsi_sextqi_7): Likewise.

Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.170
diff -u -r1.170 h8300.md
--- h8300.md	19 Feb 2003 13:00:27 -0000	1.170
+++ h8300.md	19 Feb 2003 17:42:14 -0000
@@ -2804,6 +2804,23 @@
   [(set_attr "cc" "clobber")
    (set_attr "length" "2")])
 
+(define_insn_and_split "*iorsi3_two_qi_sext"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ior:SI (zero_extend:SI (match_operand:QI 1 "register_operand" "0"))
+		(ashift:SI (sign_extend:SI (match_operand:QI 2 "register_operand" "r"))
+			   (const_int 8))))]
+  "(TARGET_H8300H || TARGET_H8300S)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 3)
+	(ior:HI (zero_extend:HI (match_dup 1))
+		(ashift:HI (match_dup 4)
+			   (const_int 8))))
+   (set (match_dup 0)
+	(sign_extend:SI (match_dup 3)))]
+  "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
+   operands[4] = gen_rtx_REG (HImode, REGNO (operands[2]));")
+
 (define_insn "*iorsi3_ashift_31"
   [(set (match_operand:SI 0 "register_operand" "=&r")
 	(ior:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
@@ -2994,6 +3011,27 @@
   "xor\\t%X1,%w0"
   [(set_attr "cc" "clobber")
    (set_attr "length" "2")])
+
+;; ashift:SI
+
+(define_insn_and_split "*ashiftsi_sextqi_7"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ashift:SI (sign_extend:SI (match_operand:QI 1 "register_operand" "0"))
+		   (const_int 7)))]
+  "(TARGET_H8300H || TARGET_H8300S)"
+  "#"
+  "&& reload_completed"
+  [(parallel [(set (match_dup 2)
+		   (ashift:HI (match_dup 2)
+			      (const_int 8)))
+	      (clobber (scratch:QI))])
+   (set (match_dup 0)
+	(sign_extend:SI (match_dup 2)))
+   (parallel [(set (match_dup 0)
+		   (ashiftrt:SI (match_dup 0)
+				(const_int 1)))
+	      (clobber (scratch:QI))])]
+  "operands[2] = gen_rtx_REG (HImode, REGNO (operands[0]));")
 
 ;; Storing a part of HImode to QImode.
 



More information about the Gcc-patches mailing list