ppc e500: fix misc patterns & add xor patterns
Aldy Hernandez
aldyh@redhat.com
Mon Feb 10 04:54:00 GMT 2003
First, the e500 assembler syntax changed back in September and redhat's
tree had a few mods that never made it out to mainline. These mods are
by Nick Clifton. I just tweaked them to make them apply.
Second, I found some xor pattern changes in my tree that will be part
of some upcoming patches, and I figured... better early than late.
Checked by building cc1 for powerpc-eabispe. I'm still putzing around
with getting an e500 sim available.
Committed to mainline.
2003-02-09 Nick Clifton <nickc@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
* config/rs6000/spe.md: spe_evlhhesplat, spe_evlhhossplat,
spe_evlhhousplat, spe_evlwhsplat, spe_evlwwsplat, spe_evldd,
spe_evldh, spe_evldw, spe_evlwhe, spe_evlwhos, spe_evlwhou,
spe_evstdd, spe_evstdh, spe_evstdw, spe_evstdwx, spe_evstwhe,
spe_evstwho, spe_evstwwe, spe_evstwwo: Fix syntax to match
newest
docs. Add range test for immediate value.
2003-02-09 Aldy Hernandez <aldyh@redhat.com>
Rename spe_evxor to xorv2si3.
(xorv4hi3): New.
(xorv1di3): New.
Index: config/rs6000/spe.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/spe.md,v
retrieving revision 1.8
diff -c -p -r1.8 spe.md
*** config/rs6000/spe.md 30 Jan 2003 13:19:16 -0000 1.8
--- config/rs6000/spe.md 10 Feb 2003 04:40:16 -0000
***************
*** 283,294 ****
(set_attr "length" "4")])
(define_insn "spe_evlhhesplat"
! [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
! (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 509)]
! "TARGET_SPE"
! "evlhhesplat %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 283,294 ----
(set_attr "length" "4")])
(define_insn "spe_evlhhesplat"
! [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
! (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 509)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlhhesplat %0,%2*2(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 307,314 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 511)]
! "TARGET_SPE"
! "evlhhossplat %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 307,314 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 511)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlhhossplat %0,%2*2(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 327,334 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 513)]
! "TARGET_SPE"
! "evlhhousplat %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 327,334 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 513)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlhhousplat %0,%2*2(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 347,354 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 515)]
! "TARGET_SPE"
! "evlwhsplat %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 347,354 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 515)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlwhsplat %0,%2*4(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 367,374 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 517)]
! "TARGET_SPE"
! "evlwwsplat %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 367,374 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 517)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlwwsplat %0,%2*4(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 581,587 ****
[(set_attr "type" "vecsimple")
(set_attr "length" "4")])
! (define_insn "spe_evxor"
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
(xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
--- 581,589 ----
[(set_attr "type" "vecsimple")
(set_attr "length" "4")])
! ;; vector xors
!
! (define_insn "xorv2si3"
[(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
(xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
(match_operand:V2SI 2 "gpc_reg_operand" "r")))]
***************
*** 590,595 ****
--- 592,617 ----
[(set_attr "type" "vecsimple")
(set_attr "length" "4")])
+ (define_insn "xorv4hi3"
+ [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
+ (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
+ (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
+ "TARGET_SPE"
+ "evxor %0,%1,%2"
+ [(set_attr "type" "vecsimple")
+ (set_attr "length" "4")])
+
+ (define_insn "xorv1di3"
+ [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
+ (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
+ (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
+ "TARGET_SPE"
+ "evxor %0,%1,%2"
+ [(set_attr "type" "vecsimple")
+ (set_attr "length" "4")])
+
+ ;; end of vector xors
+
(define_insn "spe_evfsabs"
[(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
(abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
***************
*** 747,753 ****
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 544)]
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evldd %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 769,775 ----
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 544)]
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evldd %0,%2*8(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 767,773 ****
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 546)]
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evldh %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 789,795 ----
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 546)]
"TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evldh %0,%2*8(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 786,793 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 548)]
! "TARGET_SPE"
! "evldw %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 808,815 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 548)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evldw %0,%2*8(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 806,813 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 550)]
! "TARGET_SPE"
! "evlwhe %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 828,835 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 550)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlwhe %0,%2*4(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 826,833 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 552)]
! "TARGET_SPE"
! "evlwhos %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 848,855 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 552)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlwhos %0,%2*4(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 846,853 ****
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 554)]
! "TARGET_SPE"
! "evlwhou %0,%1,%2"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
--- 868,875 ----
(mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
(match_operand:QI 2 "immediate_operand" "i"))))
(unspec [(const_int 0)] 554)]
! "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <=
31"
! "evlwhou %0,%2*4(%1)"
[(set_attr "type" "vecload")
(set_attr "length" "4")])
***************
*** 1990,1997 ****
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 686)]
! "TARGET_SPE"
! "evstdd %2,%0,%1"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
--- 2012,2019 ----
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 686)]
! "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <=
31"
! "evstdd %2,%1*8(%0)"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
***************
*** 2010,2017 ****
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 688)]
! "TARGET_SPE"
! "evstdh %2,%0,%1"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
--- 2032,2039 ----
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 688)]
! "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <=
31"
! "evstdh %2,%1*8(%0)"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
***************
*** 2030,2037 ****
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 690)]
! "TARGET_SPE"
! "evstdw %2,%0,%1"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
--- 2052,2059 ----
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 690)]
! "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <=
31"
! "evstdw %2,%1*8(%0)"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
***************
*** 2050,2057 ****
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 692)]
! "TARGET_SPE"
! "evstwhe %2,%0,%1"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
--- 2072,2079 ----
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 692)]
! "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <=
31"
! "evstwhe %2,%1*4(%0)"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
***************
*** 2070,2077 ****
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 694)]
! "TARGET_SPE"
! "evstwho %2,%0,%1"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
--- 2092,2099 ----
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 694)]
! "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <=
31"
! "evstwho %2,%1*4(%0)"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
***************
*** 2090,2097 ****
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 696)]
! "TARGET_SPE"
! "evstwwe %2,%0,%1"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
--- 2112,2119 ----
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 696)]
! "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <=
31"
! "evstwwe %2,%1*4(%0)"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
***************
*** 2110,2117 ****
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 698)]
! "TARGET_SPE"
! "evstwwo %2,%0,%1"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
--- 2132,2139 ----
(match_operand:QI 1 "immediate_operand" "i")))
(match_operand:V2SI 2 "gpc_reg_operand" "r"))
(unspec [(const_int 0)] 698)]
! "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <=
31"
! "evstwwo %2,%1*4(%0)"
[(set_attr "type" "vecstore")
(set_attr "length" "4")])
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