S/390: Remove LOAD_EXTEND_OP

[Ulrich Weigand]

Hello,

this patch gets rid of LOAD_EXTEND_OP, which isn't really
appopriate for the S/390 architecture anyway.  Instead, I'm
now using movhi/movqi expanders to decide when using an extend
operation is preferable over a QI/HImode memory load.

Bye,
Ulrich

ChangeLog:

	* config/s390/s390.h (LOAD_EXTEND_OP): Remove.
	* config/s390/s390.md ("movhi"): New expander; old insn renamed to ...
	("*movhi"): ... this.
	("movqi", "*movqi"): Likewise.
	("movqi_64"): Remove.
	("*zero_extendhisi2_31"): Change predicate to s_operand.

Index: gcc/config/s390/s390.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.h,v
retrieving revision 1.81
diff -c -p -r1.81 s390.h
*** gcc/config/s390/s390.h	21 Aug 2003 17:27:28 -0000	1.81
--- gcc/config/s390/s390.h	23 Aug 2003 15:50:53 -0000
*************** extern int s390_nr_constants;
*** 1090,1103 ****
     tablejump instruction.  */
  #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode)
  
- /* Load from integral MODE < SI from memory into register makes sign_extend
-    or zero_extend
-    In our case sign_extension happens for Halfwords, other no extension.  */
- #define LOAD_EXTEND_OP(MODE) 					\
- (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND :               \
-                  (MODE) == HImode ? SIGN_EXTEND : NIL)          \
-               : ((MODE) == HImode ? SIGN_EXTEND : NIL))
- 
  /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
     is done just by pretending it is already truncated.  */
  #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC)  1
--- 1090,1095 ----
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.69
diff -c -p -r1.69 s390.md
*** gcc/config/s390/s390.md	23 Aug 2003 15:39:18 -0000	1.69
--- gcc/config/s390/s390.md	23 Aug 2003 15:50:55 -0000
***************
*** 1295,1301 ****
  ; movhi instruction pattern(s).
  ;
  
! (define_insn "movhi"
    [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
          (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
    ""
--- 1295,1319 ----
  ; movhi instruction pattern(s).
  ;
  
! (define_expand "movhi"
!   [(set (match_operand:HI 0 "nonimmediate_operand" "")
!         (match_operand:HI 1 "general_operand" ""))]
!   ""
! {
!   /* Make it explicit that loading a register from memory 
!      always sign-extends (at least) to SImode.  */
!   if (optimize && !no_new_pseudos
!       && register_operand (operands[0], VOIDmode)
!       && memory_operand (operands[1], VOIDmode))
!     {
!       rtx tmp = gen_reg_rtx (SImode);
!       rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
!       emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
!       operands[1] = gen_lowpart (HImode, tmp);
!     }
! })
! 
! (define_insn "*movhi"
    [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
          (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
    ""
***************
*** 1324,1346 ****
  ; movqi instruction pattern(s).
  ;
  
! (define_insn "movqi_64"
!   [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,R,T,Q,S,?Q")
!         (match_operand:QI 1 "general_operand" "d,n,m,d,d,n,n,?Q"))]
!   "TARGET_64BIT"
!   "@
!    lr\t%0,%1
!    lhi\t%0,%b1
!    llgc\t%0,%1
!    stc\t%1,%0
!    stcy\t%1,%0
!    mvi\t%0,%b1
!    mviy\t%0,%b1
!    mvc\t%O0(1,%R0),%1"
!   [(set_attr "op_type" "RR,RI,RXY,RX,RXY,SI,SIY,SS")
!    (set_attr "type" "lr,*,*,store,store,store,store,cs")])
  
! (define_insn "movqi"
    [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
          (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
    ""
--- 1342,1366 ----
  ; movqi instruction pattern(s).
  ;
  
! (define_expand "movqi"
!   [(set (match_operand:QI 0 "nonimmediate_operand" "")
!         (match_operand:QI 1 "general_operand" ""))]
!   ""
! {
!   /* On 64-bit, zero-extending from memory to register
!      is just as fast as a QImode load.  */
!   if (TARGET_64BIT && optimize && !no_new_pseudos
!       && register_operand (operands[0], VOIDmode)
!       && memory_operand (operands[1], VOIDmode))
!     {
!       rtx tmp = gen_reg_rtx (DImode);
!       rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
!       emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
!       operands[1] = gen_lowpart (QImode, tmp);
!     }
! })
  
! (define_insn "*movqi"
    [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
          (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
    ""
***************
*** 2478,2484 ****
  
  (define_insn_and_split "*zero_extendhisi2_31"
    [(set (match_operand:SI 0 "register_operand" "=&d")
!         (zero_extend:SI (match_operand:HI 1 "memory_operand" "QS")))
     (clobber (reg:CC 33))]
    "!TARGET_64BIT"
    "#"
--- 2498,2504 ----
  
  (define_insn_and_split "*zero_extendhisi2_31"
    [(set (match_operand:SI 0 "register_operand" "=&d")
!         (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
     (clobber (reg:CC 33))]
    "!TARGET_64BIT"
    "#"
-- 
  Dr. Ulrich Weigand
  weigand@informatik.uni-erlangen.de