Refine when bitfield operations are used

[Alan Modra]

On Wed, Apr 16, 2003 at 05:35:34PM -0400, Richard Kenner wrote:
>         * expr.c (store_field): Force usage of bitfield instructions when
>         the field position requires it, whatever SLOW_UNALIGNED_ACCESS.
>         (expand_expr, case BIT_FIELD_REF): likewise.

On powerpc64-linux, this patch results in

+FAIL: gcc.c-torture/execute/20020227-1.c execution,  -O2
+FAIL: gcc.c-torture/execute/20020227-1.c execution,  -O3 -fomit-frame-pointer 
+FAIL: gcc.c-torture/execute/20020227-1.c execution,  -O3 -g 
+FAIL: gcc.c-torture/execute/20020227-1.c execution,  -Os 

The trouble is that "bitpos % GET_MODE_ALIGNMENT (mode)" can now
trigger when bitpos is a multiple of BITS_PER_WORD, which results in
subregs being created for access to the components of an SCmode reg.
Seems an unnecessary use of subregs to me, but not wrong in itself.

However, it exposes a subreg bug somewhere in life analysis, with the
following extract from 20020227-1.c.19.cse2

(insn 10 9 11 0 0x40080040 (set (reg/f:DI 118)
        (mem/u:DI (plus:DI (reg:DI 2 r2)
                (const:DI (minus:DI (symbol_ref/u:DI ("*.LC1") [flags 0x2])
                        (symbol_ref:DI ("*.LCTOC1"))))) [7 S8 A8])) 322 {*movdi_internal64} (nil)
    (expr_list:REG_EQUAL (symbol_ref:DI ("*.LC0") [flags 0x2])
        (nil)))

(insn 11 10 12 0 0x40080040 (clobber (reg:SC 119)) -1 (nil)
    (nil))

(insn 12 11 13 0 0x40080040 (set (reg:SF 120)
        (mem/u/f:SF (reg/f:DI 118) [2 S4 A32])) 303 {*movsf_hardfloat} (nil)
    (nil))

(insn 13 12 14 0 0x40080040 (set (subreg:SF (reg:SC 119) 0)
        (reg:SF 120)) 303 {*movsf_hardfloat} (nil)
    (nil))

(insn 14 13 15 0 0x40080040 (set (reg:SF 121)
        (mem/u/f:SF (plus:DI (reg/f:DI 118)
                (const_int 4 [0x4])) [2 S4 A32])) 303 {*movsf_hardfloat} (nil)
    (nil))

(insn 15 14 16 0 0x40080040 (set (subreg:SF (reg:SC 119) 4)
        (reg:SF 121)) 303 {*movsf_hardfloat} (nil)
    (nil))

(insn 16 15 17 0 0x40080040 (set (reg:SF 122)
        (subreg:SF (reg:SC 119) 0)) 303 {*movsf_hardfloat} (nil)
    (nil))

(insn 17 16 19 0 0x40080040 (set (mem/s:SF (plus:DI (reg/f:DI 31 r31)
                (const_int 113 [0x71])) [4 s.f+0 S4 A8])
        (reg:SF 122)) 303 {*movsf_hardfloat} (nil)
    (nil))

(insn 19 17 21 0 0x40080040 (set (mem/s:SF (plus:DI (reg/f:DI 31 r31)
                (const_int 117 [0x75])) [4 s.f+4 S4 A8])
        (reg:SF 121)) 303 {*movsf_hardfloat} (nil)
    (nil))


turning into the following from 20020227-1.c.20.life


(insn 10 9 14 0 0x40080040 (set (reg/f:DI 118)
        (mem/u:DI (plus:DI (reg:DI 2 r2)
                (const:DI (minus:DI (symbol_ref/u:DI ("*.LC1") [flags 0x2])
                        (symbol_ref:DI ("*.LCTOC1"))))) [7 S8 A8])) 322 {*movdi_internal64} (nil)
    (expr_list:REG_DEAD (reg:DI 2 r2)
        (expr_list:REG_EQUAL (symbol_ref:DI ("*.LC0") [flags 0x2])
            (nil))))

(insn 14 10 15 0 0x40080040 (set (reg:SF 121)
        (mem/u/f:SF (plus:DI (reg/f:DI 118)
                (const_int 4 [0x4])) [2 S4 A32])) 303 {*movsf_hardfloat} (insn_list 10 (nil))
    (expr_list:REG_DEAD (reg/f:DI 118)
        (nil)))

(insn 15 14 16 0 0x40080040 (set (subreg:SF (reg:SC 119) 4)
        (reg:SF 121)) 303 {*movsf_hardfloat} (insn_list 14 (nil))
    (nil))

(insn 16 15 17 0 0x40080040 (set (reg:SF 122)
        (subreg:SF (reg:SC 119) 0)) 303 {*movsf_hardfloat} (insn_list 15 (nil))
    (expr_list:REG_DEAD (reg:SC 119)
        (nil)))

(insn 17 16 19 0 0x40080040 (set (mem/s:SF (plus:DI (reg/f:DI 31 r31)
                (const_int 113 [0x71])) [4 s.f+0 S4 A8])
        (reg:SF 122)) 303 {*movsf_hardfloat} (insn_list 16 (nil))
    (expr_list:REG_DEAD (reg:SF 122)
        (nil)))

(insn 19 17 21 0 0x40080040 (set (mem/s:SF (plus:DI (reg/f:DI 31 r31)
                (const_int 117 [0x75])) [4 s.f+4 S4 A8])
        (reg:SF 121)) 303 {*movsf_hardfloat} (nil)
    (expr_list:REG_DEAD (reg:SF 121)
        (nil)))

-- 
Alan Modra
IBM OzLabs - Linux Technology Centre