[patch] doc/*.texi: Fix typos.

[Kazu Hirata]

Hi,

Attached is a patch to fix typos.  Committed as obvious.

Note that this patch does not apply to 3.3 branch.

Kazu Hirata

2003-04-13  Kazu Hirata  <kazu@cs.umass.edu>

	* doc/invoke.texi: Fix typos.
	* doc/tm.texi: Likewise.

Index: invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.264
diff -u -r1.264 invoke.texi
--- invoke.texi	12 Apr 2003 02:16:46 -0000	1.264
+++ invoke.texi	13 Apr 2003 11:08:29 -0000
@@ -2485,7 +2485,7 @@
 Taking the address of a variable which has been declared @samp{register}.
 
 @item @r{(C++ only)}
-A base class is not initialized in a derived class' copy constrcutor.
+A base class is not initialized in a derived class' copy constructor.
 @end itemize
 
 @item -Wno-div-by-zero
@@ -3915,9 +3915,9 @@
 @item -fsched2-use-superblocks
 @opindex fsched2-use-superblocks
 When schedulilng after register allocation, do use superblock scheduling
-algorithm.  Superblock scheduling allows motion acress basic block boundaries
+algorithm.  Superblock scheduling allows motion across basic block boundaries
 resulting on faster schedules.  This option is experimental, as not all machine
-descriptions used by GCC model the CPU closely enought to avoid unreliable
+descriptions used by GCC model the CPU closely enough to avoid unreliable
 results from the algorithm. 
 
 This only makes sense when scheduling after register allocation, i.e.@: with
@@ -3930,7 +3930,7 @@
 size of superblocks using tracer pass.  See @option{-ftracer} for details on
 trace formation.
 
-This mode should produce faster but singificantly longer programs.  Also
+This mode should produce faster but significantly longer programs.  Also
 without @code{-fbranch-probabilities} the traces constructed may not match the
 reality and hurt the performance.  This only makes
 sense when scheduling after register allocation, i.e.@: with
@@ -6386,7 +6386,7 @@
 is only valid if the @option{-mcpu=ep9312} option has been used to
 enable generation of instructions for the Cirrus Maverick floating
 point co-processor.  This option is not enabled by default, since the
-problem is only present in older Maverick implemenations.  The default
+problem is only present in older Maverick implementations.  The default
 can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
 switch.
 
Index: tm.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/tm.texi,v
retrieving revision 1.209
diff -u -r1.209 tm.texi
--- tm.texi	3 Apr 2003 18:23:04 -0000	1.209
+++ tm.texi	13 Apr 2003 11:08:36 -0000
@@ -5738,7 +5738,7 @@
 zero for insn passed as the parameter, the insn will be not chosen to
 be issued.
 
-The default is that any ready insns can be choosen to be issued.
+The default is that any ready insns can be chosen to be issued.
 @end deftypefn
 
 @deftypefn {Target Hook} int TARGET_SCHED_DFA_NEW_CYCLE (FILE *, int, rtx, int, int, int *)