patch applied to sh.c: Use HARD_REG_SET in prologue / epilogue code
Joern Rennecke
joern.rennecke@superh.com
Tue Apr 8 13:17:00 GMT 2003
--
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SuperH (UK) Ltd.
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2003-04-08 J"orn Rennecke <joern.rennecke@superh.com>
* sh.c (push_regs, calc_live_regs): Return int. Take single
HARD_REG_SET * parameter. Changed all callers.
Index: sh.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sh/sh.c,v
retrieving revision 1.205
diff -p -r1.205 sh.c
*** sh.c 4 Apr 2003 15:01:13 -0000 1.205
--- sh.c 8 Apr 2003 13:10:50 -0000
*************** static void output_stack_adjust PARAMS (
*** 189,196 ****
static rtx frame_insn PARAMS ((rtx));
static rtx push PARAMS ((int));
static void pop PARAMS ((int));
! static void push_regs PARAMS ((HOST_WIDE_INT *));
! static void calc_live_regs PARAMS ((int *, HOST_WIDE_INT *));
static void mark_use PARAMS ((rtx, rtx *));
static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
static rtx mark_constant_pool_use PARAMS ((rtx));
--- 189,196 ----
static rtx frame_insn PARAMS ((rtx));
static rtx push PARAMS ((int));
static void pop PARAMS ((int));
! static void push_regs PARAMS ((HARD_REG_SET *));
! static int calc_live_regs PARAMS ((HARD_REG_SET *));
static void mark_use PARAMS ((rtx, rtx *));
static HOST_WIDE_INT rounded_frame_size PARAMS ((int));
static rtx mark_constant_pool_use PARAMS ((rtx));
*************** pop (rn)
*** 4659,4665 ****
static void
push_regs (mask)
! HOST_WIDE_INT *mask;
{
int i;
--- 4659,4665 ----
static void
push_regs (mask)
! HARD_REG_SET *mask;
{
int i;
*************** push_regs (mask)
*** 4667,4689 ****
candidates for the return delay slot when there are no general
registers pushed. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
! if (i != PR_REG && mask[i / 32] & (1 << (i % 32)))
push (i);
! if (mask[PR_REG / 32] & (1 << (PR_REG % 32)))
push (PR_REG);
}
/* Work out the registers which need to be saved, both as a mask and a
! count of saved words.
If doing a pragma interrupt function, then push all regs used by the
function, and if we call another function (we can tell by looking at PR),
make sure that all the regs it clobbers are safe too. */
! static void
! calc_live_regs (count_ptr, live_regs_mask)
! int *count_ptr;
! HOST_WIDE_INT *live_regs_mask;
{
int reg;
int count;
--- 4667,4688 ----
candidates for the return delay slot when there are no general
registers pushed. */
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
! if (i != PR_REG && TEST_HARD_REG_BIT (*mask, i))
push (i);
! if (TEST_HARD_REG_BIT (*mask, PR_REG))
push (PR_REG);
}
/* Work out the registers which need to be saved, both as a mask and a
! count of saved words. Return the count.
If doing a pragma interrupt function, then push all regs used by the
function, and if we call another function (we can tell by looking at PR),
make sure that all the regs it clobbers are safe too. */
! static int
! calc_live_regs (live_regs_mask)
! HARD_REG_SET *live_regs_mask;
{
int reg;
int count;
*************** calc_live_regs (count_ptr, live_regs_mas
*** 4693,4699 ****
interrupt_handler = sh_cfun_interrupt_handler_p ();
for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
! live_regs_mask[count] = 0;
/* If we can save a lot of saves by switching to double mode, do that. */
if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
--- 4692,4698 ----
interrupt_handler = sh_cfun_interrupt_handler_p ();
for (count = 0; 32 * count < FIRST_PSEUDO_REGISTER; count++)
! CLEAR_HARD_REG_SET (*live_regs_mask);
/* If we can save a lot of saves by switching to double mode, do that. */
if (TARGET_SH4 && TARGET_FMOVD && TARGET_FPU_SINGLE)
for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
*************** calc_live_regs (count_ptr, live_regs_mas
*** 4752,4758 ****
|| reg == EH_RETURN_DATA_REGNO (2)
|| reg == EH_RETURN_DATA_REGNO (3)))))
{
! live_regs_mask[reg / 32] |= 1 << (reg % 32);
count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
--- 4751,4757 ----
|| reg == EH_RETURN_DATA_REGNO (2)
|| reg == EH_RETURN_DATA_REGNO (3)))))
{
! SET_HARD_REG_BIT (*live_regs_mask, reg);
count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
if ((TARGET_SH4 || TARGET_SH5) && TARGET_FMOVD
*************** calc_live_regs (count_ptr, live_regs_mas
*** 4762,4768 ****
{
if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
{
! live_regs_mask[(reg ^ 1) / 32] |= 1 << ((reg ^ 1) % 32);
count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
}
}
--- 4761,4767 ----
{
if (! TARGET_FPU_SINGLE && ! regs_ever_live[reg ^ 1])
{
! SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
}
}
*************** calc_live_regs (count_ptr, live_regs_mas
*** 4775,4781 ****
}
}
! *count_ptr = count;
}
/* Code to generate prologue and epilogue sequences */
--- 4774,4780 ----
}
}
! return count;
}
/* Code to generate prologue and epilogue sequences */
*************** sh_media_register_for_return ()
*** 4817,4823 ****
void
sh_expand_prologue ()
{
! HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
int d, i;
int d_rounding = 0;
int save_flags = target_flags;
--- 4816,4822 ----
void
sh_expand_prologue ()
{
! HARD_REG_SET live_regs_mask;
int d, i;
int d_rounding = 0;
int save_flags = target_flags;
*************** sh_expand_prologue ()
*** 4909,4915 ****
if (sp_switch)
emit_insn (gen_sp_switch_1 ());
! calc_live_regs (&d, live_regs_mask);
/* ??? Maybe we could save some switching if we can move a mode switch
that already happens to be at the function start into the prologue. */
if (target_flags != save_flags)
--- 4908,4914 ----
if (sp_switch)
emit_insn (gen_sp_switch_1 ());
! d = calc_live_regs (&live_regs_mask);
/* ??? Maybe we could save some switching if we can move a mode switch
that already happens to be at the function start into the prologue. */
if (target_flags != save_flags)
*************** sh_expand_prologue ()
*** 4940,4946 ****
sh_expand_epilogue, but also sh_set_return_address. */
for (align = 1; align >= 0; align--)
for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
! if (live_regs_mask[i/32] & (1 << (i % 32)))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
int reg = i;
--- 4939,4945 ----
sh_expand_epilogue, but also sh_set_return_address. */
for (align = 1; align >= 0; align--)
for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
! if (TEST_HARD_REG_BIT (live_regs_mask, i))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
int reg = i;
*************** sh_expand_prologue ()
*** 4948,4954 ****
if (mode == SFmode && (i % 2) == 1
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
{
mode = DFmode;
i--;
--- 4947,4953 ----
if (mode == SFmode && (i % 2) == 1
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && (TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1))))
{
mode = DFmode;
i--;
*************** sh_expand_prologue ()
*** 5069,5075 ****
abort ();
}
else
! push_regs (live_regs_mask);
if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
{
--- 5068,5074 ----
abort ();
}
else
! push_regs (&live_regs_mask);
if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
{
*************** sh_expand_prologue ()
*** 5138,5151 ****
void
sh_expand_epilogue ()
{
! HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
int d, i;
int d_rounding = 0;
int save_flags = target_flags;
int frame_size;
! calc_live_regs (&d, live_regs_mask);
if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT))
d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
--- 5137,5150 ----
void
sh_expand_epilogue ()
{
! HARD_REG_SET live_regs_mask;
int d, i;
int d_rounding = 0;
int save_flags = target_flags;
int frame_size;
! d = calc_live_regs (&live_regs_mask);
if (TARGET_SH5 && d % (STACK_BOUNDARY / BITS_PER_UNIT))
d_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
*************** sh_expand_epilogue ()
*** 5206,5212 ****
alignment. */
for (align = 0; align <= 1; align++)
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
! if (live_regs_mask[i/32] & (1 << (i % 32)))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
int reg = i;
--- 5205,5211 ----
alignment. */
for (align = 0; align <= 1; align++)
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
! if (TEST_HARD_REG_BIT (live_regs_mask, i))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
int reg = i;
*************** sh_expand_epilogue ()
*** 5214,5220 ****
if (mode == SFmode && (i % 2) == 0
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
{
mode = DFmode;
i++;
--- 5213,5219 ----
if (mode == SFmode && (i % 2) == 0
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && (TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1))))
{
mode = DFmode;
i++;
*************** sh_expand_epilogue ()
*** 5336,5348 ****
}
else
d = 0;
! if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
pop (PR_REG);
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
int j = (FIRST_PSEUDO_REGISTER - 1) - i;
! if (j != PR_REG && live_regs_mask[j / 32] & (1 << (j % 32)))
pop (j);
}
finish:
--- 5335,5347 ----
}
else
d = 0;
! if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
pop (PR_REG);
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
{
int j = (FIRST_PSEUDO_REGISTER - 1) - i;
! if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j))
pop (j);
}
finish:
*************** sh_expand_epilogue ()
*** 5367,5373 ****
/* PR_REG will never be live in SHmedia mode, and we don't need to
USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
by the return pattern. */
! if (live_regs_mask[PR_REG / 32] & (1 << (PR_REG % 32)))
emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
}
--- 5366,5372 ----
/* PR_REG will never be live in SHmedia mode, and we don't need to
USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
by the return pattern. */
! if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, PR_REG)));
}
*************** void
*** 5396,5412 ****
sh_set_return_address (ra, tmp)
rtx ra, tmp;
{
! HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
int d;
int d_rounding = 0;
int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
int pr_offset;
! calc_live_regs (&d, live_regs_mask);
/* If pr_reg isn't life, we can set it (or the register given in
sh_media_register_for_return) directly. */
! if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
{
rtx rr;
--- 5395,5411 ----
sh_set_return_address (ra, tmp)
rtx ra, tmp;
{
! HARD_REG_SET live_regs_mask;
int d;
int d_rounding = 0;
int pr_reg = TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG;
int pr_offset;
! d = calc_live_regs (&live_regs_mask);
/* If pr_reg isn't life, we can set it (or the register given in
sh_media_register_for_return) directly. */
! if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
{
rtx rr;
*************** sh_set_return_address (ra, tmp)
*** 5446,5458 ****
alignment. */
for (align = 0; align <= 1; align++)
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
! if (live_regs_mask[i/32] & (1 << (i % 32)))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
if (mode == SFmode && (i % 2) == 0
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && (live_regs_mask[(i ^ 1) / 32] & (1 << ((i ^ 1) % 32))))
{
mode = DFmode;
i++;
--- 5445,5457 ----
alignment. */
for (align = 0; align <= 1; align++)
for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
! if (TEST_HARD_REG_BIT (live_regs_mask, i))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
if (mode == SFmode && (i % 2) == 0
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && (TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1))))
{
mode = DFmode;
i++;
*************** initial_elimination_offset (from, to)
*** 5931,5938 ****
int save_flags = target_flags;
int copy_flags;
! HOST_WIDE_INT live_regs_mask[(FIRST_PSEUDO_REGISTER + 31) / 32];
! calc_live_regs (®s_saved, live_regs_mask);
regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
--- 5930,5937 ----
int save_flags = target_flags;
int copy_flags;
! HARD_REG_SET live_regs_mask;
! regs_saved = calc_live_regs (&live_regs_mask);
regs_saved += SHMEDIA_REGS_STACK_ADJUST ();
if (TARGET_SH5 && regs_saved % (STACK_BOUNDARY / BITS_PER_UNIT))
regs_saved_rounding = ((STACK_BOUNDARY / BITS_PER_UNIT)
*************** initial_elimination_offset (from, to)
*** 5968,5974 ****
n += total_auto_space;
/* If it wasn't saved, there's not much we can do. */
! if ((live_regs_mask[pr_reg / 32] & (1 << (pr_reg % 32))) == 0)
return n;
target_flags = copy_flags;
--- 5967,5973 ----
n += total_auto_space;
/* If it wasn't saved, there's not much we can do. */
! if (! TEST_HARD_REG_BIT (live_regs_mask, pr_reg))
return n;
target_flags = copy_flags;
*************** initial_elimination_offset (from, to)
*** 5979,5992 ****
need 8-byte alignment. */
for (align = 1; align >= 0; align--)
for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
! if (live_regs_mask[i/32] & (1 << (i % 32)))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
if (mode == SFmode && (i % 2) == 1
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && (live_regs_mask[(i ^ 1) / 32]
! & (1 << ((i ^ 1) % 32))))
{
mode = DFmode;
i--;
--- 5978,5990 ----
need 8-byte alignment. */
for (align = 1; align >= 0; align--)
for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
! if (TEST_HARD_REG_BIT (live_regs_mask, i))
{
enum machine_mode mode = REGISTER_NATURAL_MODE (i);
if (mode == SFmode && (i % 2) == 1
&& ! TARGET_FPU_SINGLE && FP_REGISTER_P (i)
! && TEST_HARD_REG_BIT (live_regs_mask, (i ^ 1)))
{
mode = DFmode;
i--;
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