ppc e500: option to disable SPE SIMD
Aldy Hernandez
aldyh@redhat.com
Mon Apr 7 02:47:00 GMT 2003
This patch adds the option -mspe=yes/no to enable/disable SPE.
I have also added TARGET_E500, and tweaked the back end to separate the
concept of SIMD SPE from having an e500. An E500 is the 8540, but it
may be possible to have an 8540 and it not have SIMD (SPE) operations.
Regtested on powerpc-eabispe.
Committed to mainline.
2003-04-06 Aldy Hernandez <aldyh@redhat.com>
* doc/invoke.texi (RS/6000 and PowerPC Options): Document -mspe
option.
* config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Set
rs6000_spe.
* config/rs6000/eabi.h (TARGET_E500): Define.
* config/rs6000/rs6000.h (TARGET_E500): Define.
(TARGET_OPTIONS): Add spe= option.
Declare rs6000_spe and rs6000_spe_string extern.
* config/rs6000/rs6000.c (branch_positive_comparison_operator):
Change TARGET_SPE to TARGET_E500.
(ccr_bit): Change TARGET_SPE to TARGET_E500. Check for
!TARGET_FPRS.
(print_operand): Same.
(rs6000_generate_compare): Same.
(output_cbranch): Same.
(rs6000_spe): Declare.
(rs6000_spe_string): Declare.
(rs6000_override_options): Call rs6000_parse_spe_option.
(rs6000_parse_spe_option): New.
Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.256
diff -c -p -r1.256 invoke.texi
*** doc/invoke.texi 2 Apr 2003 07:08:15 -0000 1.256
--- doc/invoke.texi 7 Apr 2003 02:43:09 -0000
*************** in the following sections.
*** 447,452 ****
--- 447,453 ----
-mabi=altivec -mabi=no-altivec @gol
-mabi=spe -mabi=no-spe @gol
-misel=yes -misel=no @gol
+ -mspe=yes -mspe=no @gol
-mprototype -mno-prototype @gol
-msim -mmvme -mads -myellowknife -memb -msdata @gol
-msdata=@var{opt} -mvxworks -mwindiss -G @var{num} -pthread}
*************** Disable Booke SPE ABI extensions for the
*** 7027,7032 ****
--- 7028,7039 ----
@itemx -misel
@opindex misel
This switch enables or disables the generation of ISEL instructions.
+
+ @item -mspe=@var{yes/no}
+ @itemx -mspe
+ @opindex mspe
+ This switch enables or disables the generation of SPE simd
+ instructions.
@item -mfull-toc
@itemx -mno-fp-in-toc
Index: config/rs6000/eabispe.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/eabispe.h,v
retrieving revision 1.2
diff -c -p -r1.2 eabispe.h
*** config/rs6000/eabispe.h 11 Feb 2003 00:13:24 -0000 1.2
--- config/rs6000/eabispe.h 7 Apr 2003 02:43:09 -0000
*************** Boston, MA 02111-1307, USA. */
*** 36,41 ****
--- 36,43 ----
/* See note below. */ \
/*if (rs6000_long_double_size_string == NULL)*/ \
/* rs6000_long_double_type_size = 128;*/ \
+ if (rs6000_spe_string == NULL) \
+ rs6000_spe = 1; \
if (rs6000_isel_string == NULL) \
rs6000_isel = 1
Index: config/rs6000/eabi.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/eabi.h,v
retrieving revision 1.7
diff -c -p -r1.7 eabi.h
*** config/rs6000/eabi.h 25 Jul 2002 02:22:47 -0000 1.7
--- config/rs6000/eabi.h 7 Apr 2003 02:43:09 -0000
*************** Boston, MA 02111-1307, USA. */
*** 45,54 ****
#undef TARGET_SPE_ABI
#undef TARGET_SPE
#undef TARGET_ISEL
#undef TARGET_FPRS
#define TARGET_SPE_ABI rs6000_spe_abi
! #define TARGET_SPE (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_ISEL rs6000_isel
#define TARGET_FPRS rs6000_fprs
--- 45,56 ----
#undef TARGET_SPE_ABI
#undef TARGET_SPE
+ #undef TARGET_E500
#undef TARGET_ISEL
#undef TARGET_FPRS
#define TARGET_SPE_ABI rs6000_spe_abi
! #define TARGET_SPE rs6000_spe
! #define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_ISEL rs6000_isel
#define TARGET_FPRS rs6000_fprs
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.261
diff -c -p -r1.261 rs6000.h
*** config/rs6000/rs6000.h 1 Apr 2003 13:40:11 -0000 1.261
--- config/rs6000/rs6000.h 7 Apr 2003 02:43:09 -0000
*************** extern enum processor_type rs6000_cpu;
*** 388,393 ****
--- 388,395 ----
N_("Specify size of long double (64 or 128 bits)") }, \
{"isel=", &rs6000_isel_string,
\
N_("Specify yes/no if isel instructions should be generated") },
\
+ {"spe=", &rs6000_spe_string,
\
+ N_("Specify yes/no if SPE SIMD instructions should be generated")
},\
{"vrsave=", &rs6000_altivec_vrsave_string,
\
N_("Specify yes/no if VRSAVE instructions should be generated for
AltiVec") }, \
{"longcall", &rs6000_longcall_switch, \
*************** extern int rs6000_long_double_type_size;
*** 425,432 ****
--- 427,436 ----
extern int rs6000_altivec_abi;
extern int rs6000_spe_abi;
extern int rs6000_isel;
+ extern int rs6000_spe;
extern int rs6000_fprs;
extern const char *rs6000_isel_string;
+ extern const char *rs6000_spe_string;
extern const char *rs6000_altivec_vrsave_string;
extern int rs6000_altivec_vrsave;
extern const char *rs6000_longcall_switch;
*************** extern int rs6000_default_long_calls;
*** 438,443 ****
--- 442,448 ----
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
+ #define TARGET_E500 0
#define TARGET_ISEL 0
#define TARGET_FPRS 1
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.450
diff -c -p -r1.450 rs6000.c
*** config/rs6000/rs6000.c 5 Apr 2003 17:07:58 -0000 1.450
--- config/rs6000/rs6000.c 7 Apr 2003 02:43:10 -0000
*************** int rs6000_spe_abi;
*** 95,106 ****
--- 95,112 ----
/* Whether isel instructions should be generated. */
int rs6000_isel;
+ /* Whether SPE simd instructions should be generated. */
+ int rs6000_spe;
+
/* Nonzero if we have FPRs. */
int rs6000_fprs = 1;
/* String from -misel=. */
const char *rs6000_isel_string;
+ /* String from -mspe=. */
+ const char *rs6000_spe_string;
+
/* Set to nonzero once AIX common-mode calls have been defined. */
static GTY(()) int common_mode_defined;
*************** static rtx altivec_expand_stv_builtin PA
*** 270,275 ****
--- 276,282 ----
static void rs6000_parse_abi_options PARAMS ((void));
static void rs6000_parse_vrsave_option PARAMS ((void));
static void rs6000_parse_isel_option PARAMS ((void));
+ static void rs6000_parse_spe_option (void);
static int first_altivec_reg_to_save PARAMS ((void));
static unsigned int compute_vrsave_mask PARAMS ((void));
static void is_altivec_return_reg PARAMS ((rtx, void *));
*************** rs6000_override_options (default_cpu)
*** 612,618 ****
}
}
! if (rs6000_cpu == PROCESSOR_PPC8540)
rs6000_isel = 1;
/* If we are optimizing big endian systems for space, use the
load/store
--- 619,625 ----
}
}
! if (TARGET_E500)
rs6000_isel = 1;
/* If we are optimizing big endian systems for space, use the
load/store
*************** rs6000_override_options (default_cpu)
*** 701,706 ****
--- 708,716 ----
/* Handle -misel= option. */
rs6000_parse_isel_option ();
+ /* Handle -mspe= option. */
+ rs6000_parse_spe_option ();
+
#ifdef SUBTARGET_OVERRIDE_OPTIONS
SUBTARGET_OVERRIDE_OPTIONS;
#endif
*************** rs6000_parse_isel_option ()
*** 788,793 ****
--- 798,817 ----
rs6000_isel_string);
}
+ /* Handle -mspe= option. */
+ static void
+ rs6000_parse_spe_option (void)
+ {
+ if (rs6000_spe_string == 0)
+ return;
+ else if (!strcmp (rs6000_spe_string, "yes"))
+ rs6000_spe = 1;
+ else if (!strcmp (rs6000_spe_string, "no"))
+ rs6000_spe = 0;
+ else
+ error ("unknown -mspe= option specified: '%s'",
rs6000_spe_string);
+ }
+
/* Handle -mvrsave= options. */
static void
rs6000_parse_vrsave_option ()
*************** branch_positive_comparison_operator (op,
*** 7009,7015 ****
code = GET_CODE (op);
return (code == EQ || code == LT || code == GT
! || (TARGET_SPE && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
|| code == LTU || code == GTU
|| code == UNORDERED);
}
--- 7033,7039 ----
code = GET_CODE (op);
return (code == EQ || code == LT || code == GT
! || (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE)
|| code == LTU || code == GTU
|| code == UNORDERED);
}
*************** ccr_bit (op, scc_p)
*** 7469,7479 ****
switch (code)
{
case NE:
! if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
return base_bit + 1;
return scc_p ? base_bit + 3 : base_bit + 2;
case EQ:
! if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
return base_bit + 1;
return base_bit + 2;
case GT: case GTU: case UNLE:
--- 7493,7505 ----
switch (code)
{
case NE:
! if (TARGET_E500 && !TARGET_FPRS
! && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
return base_bit + 1;
return scc_p ? base_bit + 3 : base_bit + 2;
case EQ:
! if (TARGET_E500 && !TARGET_FPRS
! && TARGET_HARD_FLOAT && cc_mode == CCFPmode)
return base_bit + 1;
return base_bit + 2;
case GT: case GTU: case UNLE:
*************** print_operand (file, x, code)
*** 7685,7691 ****
fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
base_bit + 2, base_bit + 2);
}
! else if (TARGET_SPE && TARGET_HARD_FLOAT
&& GET_CODE (x) == EQ
&& GET_MODE (XEXP (x, 0)) == CCFPmode)
{
--- 7711,7717 ----
fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3,
base_bit + 2, base_bit + 2);
}
! else if (TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT
&& GET_CODE (x) == EQ
&& GET_MODE (XEXP (x, 0)) == CCFPmode)
{
*************** print_operand (file, x, code)
*** 8192,8198 ****
tmp = XEXP (x, 0);
! if (TARGET_SPE)
{
/* Handle [reg]. */
if (GET_CODE (tmp) == REG)
--- 8218,8224 ----
tmp = XEXP (x, 0);
! if (TARGET_E500)
{
/* Handle [reg]. */
if (GET_CODE (tmp) == REG)
*************** rs6000_generate_compare (code)
*** 8477,8483 ****
compare_result = gen_reg_rtx (comp_mode);
/* SPE FP compare instructions on the GPRs. Yuck! */
! if ((TARGET_SPE && TARGET_HARD_FLOAT) && rs6000_compare_fp_p)
{
rtx cmp, or1, or2, or_result, compare_result2;
--- 8503,8510 ----
compare_result = gen_reg_rtx (comp_mode);
/* SPE FP compare instructions on the GPRs. Yuck! */
! if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
! && rs6000_compare_fp_p)
{
rtx cmp, or1, or2, or_result, compare_result2;
*************** rs6000_generate_compare (code)
*** 8602,8608 ****
except for flag_unsafe_math_optimizations we don't bother. */
if (rs6000_compare_fp_p
&& ! flag_unsafe_math_optimizations
! && ! (TARGET_HARD_FLOAT && TARGET_SPE)
&& (code == LE || code == GE
|| code == UNEQ || code == LTGT
|| code == UNGT || code == UNLT))
--- 8629,8635 ----
except for flag_unsafe_math_optimizations we don't bother. */
if (rs6000_compare_fp_p
&& ! flag_unsafe_math_optimizations
! && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
&& (code == LE || code == GE
|| code == UNEQ || code == LTGT
|| code == UNGT || code == UNLT))
*************** output_cbranch (op, label, reversed, ins
*** 8730,8736 ****
code = reverse_condition (code);
}
! if ((TARGET_SPE && TARGET_HARD_FLOAT) && mode == CCFPmode)
{
/* The efscmp/tst* instructions twiddle bit 2, which maps nicely
to the GT bit. */
--- 8757,8763 ----
code = reverse_condition (code);
}
! if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode ==
CCFPmode)
{
/* The efscmp/tst* instructions twiddle bit 2, which maps nicely
to the GT bit. */
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