[PATCH/RFA] ARM MASK_RETURN_ADDR fix for mixed 26/32-bit

[Jason R Thorpe]

On Thu, Sep 05, 2002 at 11:11:10AM +0100, Richard Earnshaw wrote:

 > The patch needs to be fixed to work with -mthumb before this can go in.  
 > For that case it should always return ~0 (Since I think we need to 
 > preserve the Thumb bit in this case).

Something as simple as just testing for TARGET_TUMB in addition to
arm_arch4?

(I'm pretty sure the run-time test would have also worked for Thumb, but
it's certainly true that if you're using Thumb, you're not running in 26-bit
mode :-)

        * config/arm/arm-protos.h (arm_gen_return_addr_mask): New
        prototype.
        * config/arm/arm.c (arm_gen_return_addr_mask): New function.
        * config/arm/arm.h (MASK_RETURN_ADDR): Use arm_gen_return_addr_mask
        if not APCS26 and not Thumb or ARMv4-or-higher.
        * config/arm/arm.md (UNSPEC_CHECK_ARCH): Define.
        (return_addr_mask, *check_arch2): New.

-- 
        -- Jason R. Thorpe <thorpej@wasabisystems.com>
-------------- next part --------------
Index: config/arm/arm-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm-protos.h,v
retrieving revision 1.31
diff -c -r1.31 arm-protos.h
*** config/arm/arm-protos.h	5 Sep 2002 16:45:24 -0000	1.31
--- config/arm/arm-protos.h	5 Sep 2002 18:51:54 -0000
***************
*** 107,112 ****
--- 107,113 ----
  extern rtx    arm_gen_rotated_half_load	PARAMS ((rtx));
  extern enum machine_mode arm_select_cc_mode PARAMS ((RTX_CODE, rtx, rtx));
  extern rtx    arm_gen_compare_reg	PARAMS ((RTX_CODE, rtx, rtx));
+ extern rtx    arm_gen_return_addr_mask	PARAMS ((void));
  extern void   arm_reload_in_hi		PARAMS ((rtx *));
  extern void   arm_reload_out_hi		PARAMS ((rtx *));
  extern void   arm_reorg			PARAMS ((rtx));
Index: config/arm/arm.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.226
diff -c -r1.226 arm.c
*** config/arm/arm.c	5 Sep 2002 17:11:47 -0000	1.226
--- config/arm/arm.c	5 Sep 2002 18:52:02 -0000
***************
*** 4914,4919 ****
--- 4914,4932 ----
    return cc_reg;
  }
  
+ /* Generate a sequence of insns that will generate the correct return
+    address mask depending on the physical architecture that the program
+    is running on.  */
+ 
+ rtx
+ arm_gen_return_addr_mask ()
+ {
+   rtx reg = gen_reg_rtx (Pmode);
+ 
+   emit_insn (gen_return_addr_mask (reg));
+   return reg;
+ }
+ 
  void
  arm_reload_in_hi (operands)
       rtx * operands;
Index: config/arm/arm.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.158
diff -c -r1.158 arm.h
*** config/arm/arm.h	5 Sep 2002 17:11:47 -0000	1.158
--- config/arm/arm.h	5 Sep 2002 18:52:05 -0000
***************
*** 2754,2760 ****
       return address.  This does not apply to ARM6 and later processors	\
       when running in 32 bit mode.  */					\
    ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26))			\
!    : (GEN_INT ((unsigned long)0xffffffff)))
  
  
  /* Define the codes that are matched by predicates in arm.c */
--- 2754,2761 ----
       return address.  This does not apply to ARM6 and later processors	\
       when running in 32 bit mode.  */					\
    ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26))			\
!    : (arm_arch4 || TARGET_THUMB) ? (GEN_INT ((unsigned long)0xffffffff))\
!    : arm_gen_return_addr_mask ())
  
  
  /* Define the codes that are matched by predicates in arm.c */
Index: config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.104
diff -c -r1.104 arm.md
*** config/arm/arm.md	29 Jul 2002 12:41:46 -0000	1.104
--- config/arm/arm.md	5 Sep 2002 18:52:12 -0000
***************
*** 69,74 ****
--- 69,75 ----
     			; instructions setting registers for EH handling
     			; and stack frame generation.  Operand 0 is the
     			; register to "use".
+    (UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode.
    ]
  )
  
***************
*** 6795,6800 ****
--- 6796,6828 ----
    }"
    [(set_attr "conds" "use")
     (set_attr "type" "load")]
+ )
+ 
+ ;; Generate a sequence of instructions to determine if the processor is
+ ;; in 26-bit or 32-bit mode, and return the appropriate return address
+ ;; mask.
+ 
+ (define_expand "return_addr_mask"
+   [(set (match_dup 1)
+       (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ 		       (const_int 0)))
+    (set (match_operand:SI 0 "s_register_operand" "")
+       (if_then_else:SI (eq (match_dup 1) (const_int 0))
+ 		       (const_int -1)
+ 		       (const_int 67108860)))] ; 0x03fffffc
+   ""
+   "
+   operands[1] = gen_rtx_REG (CC_NOOVmode, 24);
+   ")
+ 
+ (define_insn "*check_arch2"
+   [(set (match_operand:CC_NOOV 0 "cc_register" "")
+       (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH)
+ 		       (const_int 0)))]
+   ""
+   "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc"
+   [(set_attr "length" "8")
+    (set_attr "conds" "set")]
  )
  
  ;; Call subroutine returning any type.