[PATCH] allow DFmode in CTR/LR on PowerPC
David Edelsohn
dje@watson.ibm.com
Fri Oct 18 21:39:00 GMT 2002
This is the 64-bit equivalent to Geoff's earlier patch, plus a
little cleanup.
David
* rs6000.md (movdf_hardfloat32): Order alternatives consistently.
Use length of 4 not *.
(movdf_hardfloat64): Same. Support DFmode moves to/from CTR/LR.
(movdf_softfloat64): Likewise.
(movdi_internal32): Use length of 4 not *.
(movti_power): Same.
(ctrsi, ctrdi): Same.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.217
diff -c -p -r1.217 rs6000.md
*** rs6000.md 18 Oct 2002 00:30:23 -0000 1.217
--- rs6000.md 19 Oct 2002 03:25:22 -0000
***************
*** 8541,8548 ****
;; The "??" is a kludge until we can figure out a more reasonable way
;; of handling these non-offsettable values.
(define_insn "*movdf_hardfloat32"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
! (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
--- 8541,8548 ----
;; The "??" is a kludge until we can figure out a more reasonable way
;; of handling these non-offsettable values.
(define_insn "*movdf_hardfloat32"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
! (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
***************
*** 8619,8637 ****
return \"\";
}
case 3:
case 4:
case 5:
! return \"#\";
case 6:
- return \"fmr %0,%1\";
case 7:
- return \"lfd%U1%X1 %0,%1\";
case 8:
! return \"stfd%U0%X0 %1,%0\";
}
}"
! [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
! (set_attr "length" "8,16,16,8,12,16,*,*,*")])
(define_insn "*movdf_softfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
--- 8619,8637 ----
return \"\";
}
case 3:
+ return \"fmr %0,%1\";
case 4:
+ return \"lfd%U1%X1 %0,%1\";
case 5:
! return \"stfd%U0%X0 %1,%0\";
case 6:
case 7:
case 8:
! return \"#\";
}
}"
! [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
! (set_attr "length" "8,16,16,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat32"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
***************
*** 8675,8682 ****
(set_attr "length" "8,8,8,8,12,16")])
(define_insn "*movdf_hardfloat64"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
! (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
--- 8675,8682 ----
(set_attr "length" "8,8,8,8,12,16")])
(define_insn "*movdf_hardfloat64"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r")
! (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
***************
*** 8684,8713 ****
mr %0,%1
ld%U1%X1 %0,%1
std%U0%X0 %1,%0
- #
- #
- #
fmr %0,%1
lfd%U1%X1 %0,%1
! stfd%U0%X0 %1,%0"
! [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
! (set_attr "length" "4,4,4,8,12,16,4,4,4")])
(define_insn "*movdf_softfloat64"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
! (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
"TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"@
mr %0,%1
ld%U1%X1 %0,%1
std%U0%X0 %1,%0
#
#
#"
! [(set_attr "type" "*,load,store,*,*,*")
! (set_attr "length" "*,*,*,8,12,16")])
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
--- 8684,8717 ----
mr %0,%1
ld%U1%X1 %0,%1
std%U0%X0 %1,%0
fmr %0,%1
lfd%U1%X1 %0,%1
! stfd%U0%X0 %1,%0
! mt%0 %1
! mf%1 %0
! #
! #
! #"
! [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
! (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
(define_insn "*movdf_softfloat64"
! [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r")
! (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))]
"TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
&& (gpc_reg_operand (operands[0], DFmode)
|| gpc_reg_operand (operands[1], DFmode))"
"@
mr %0,%1
+ mt%0 %1
+ mf%1 %0
ld%U1%X1 %0,%1
std%U0%X0 %1,%0
#
#
#"
! [(set_attr "type" "*,*,*,load,store,*,*,*")
! (set_attr "length" "4,4,4,4,4,8,12,16")])
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")
***************
*** 9026,9032 ****
}
}"
[(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
! (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
--- 9030,9036 ----
}
}"
[(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
! (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")])
(define_split
[(set (match_operand:DI 0 "gpc_reg_operand" "")
***************
*** 9241,9247 ****
}
}"
[(set_attr "type" "store,store,*,load,load")
! (set_attr "length" "*,16,16,*,16")])
(define_insn "*movti_string"
[(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
--- 9245,9251 ----
}
}"
[(set_attr "type" "store,store,*,load,load")
! (set_attr "length" "4,16,16,4,16")])
(define_insn "*movti_string"
[(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
***************
*** 14153,14159 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrsi_internal2"
[(set (pc)
--- 14157,14163 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrsi_internal2"
[(set (pc)
***************
*** 14177,14183 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal1"
[(set (pc)
--- 14181,14187 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal1"
[(set (pc)
***************
*** 14201,14207 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal2"
[(set (pc)
--- 14205,14211 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal2"
[(set (pc)
***************
*** 14225,14231 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
;; Similar, but we can use GE since we have a REG_NONNEG.
--- 14229,14235 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
;; Similar, but we can use GE since we have a REG_NONNEG.
***************
*** 14251,14257 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrsi_internal4"
[(set (pc)
--- 14255,14261 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrsi_internal4"
[(set (pc)
***************
*** 14275,14281 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal3"
[(set (pc)
--- 14279,14285 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal3"
[(set (pc)
***************
*** 14299,14305 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal4"
[(set (pc)
--- 14303,14309 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal4"
[(set (pc)
***************
*** 14323,14329 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
;; Similar but use EQ
--- 14327,14333 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
;; Similar but use EQ
***************
*** 14349,14355 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrsi_internal6"
[(set (pc)
--- 14353,14359 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrsi_internal6"
[(set (pc)
***************
*** 14373,14379 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal5"
[(set (pc)
--- 14377,14383 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal5"
[(set (pc)
***************
*** 14397,14403 ****
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
(define_insn "*ctrdi_internal6"
[(set (pc)
--- 14401,14407 ----
return \"{bdn|bdnz} $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
(define_insn "*ctrdi_internal6"
[(set (pc)
***************
*** 14421,14427 ****
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "*,12,16")])
;; Now the splitters if we could not allocate the CTR register
--- 14425,14431 ----
return \"bdz $+8\;b %l0\";
}"
[(set_attr "type" "branch")
! (set_attr "length" "4,12,16")])
;; Now the splitters if we could not allocate the CTR register
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