[3.4-BIB] Optimize cvtsd2ss for Athlon/K8
Jan Hubicka
jh@suse.cz
Tue Nov 26 14:14:00 GMT 2002
Hi,
As a special case xorps is not needed in front of cvtsd2ss instruction on Athlon.
Fri Nov 22 19:58:19 CET 2002 Jan Hubicka <jh@suse.cz>
* i386.md (truncdfsf patterns and splitters): Do not generate xorps for athlon.
*** ../i386.md Tue Nov 26 19:57:39 2002
--- i386.md Tue Nov 26 23:00:15 2002
***************
*** 3801,3807 ****
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
! "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS"
{
switch (which_alternative)
{
--- 3801,3810 ----
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
! "TARGET_80387 && TARGET_SSE2
! /* Athlon optimizes partial-register FPS special case, thus avoiding the
! need for extra instructions beforehand */
! && (!TARGET_SSE_PARTIAL_REGS || TARGET_ATHLON_K8)"
{
switch (which_alternative)
{
***************
*** 3824,3830 ****
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
! "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS"
{
switch (which_alternative)
{
--- 3827,3836 ----
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "f#Y,f#Y,f#Y,f#Y,mY#f")))
(clobber (match_operand:SF 2 "memory_operand" "=X,m,m,m,X"))]
! "TARGET_80387 && TARGET_SSE2
! /* Athlon optimizes partial-register FPS special case, thus avoiding the
! need for extra instructions beforehand */
! && TARGET_SSE_PARTIAL_REGS && !TARGET_ATHLON_K8"
{
switch (which_alternative)
{
***************
*** 3846,3852 ****
[(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY,f#Y")))]
! "TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
--- 3852,3861 ----
[(set (match_operand:SF 0 "nonimmediate_operand" "=Y,!m")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY,f#Y")))]
! "TARGET_80387 && TARGET_SSE2
! /* Athlon optimizes partial-register FPS special case, thus avoiding the
! need for extra instructions beforehand */
! && (!TARGET_SSE_PARTIAL_REGS || TARGET_ATHLON_K8)
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
***************
*** 3869,3875 ****
[(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
! "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
--- 3878,3887 ----
[(set (match_operand:SF 0 "nonimmediate_operand" "=&Y,!m")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY,f")))]
! "TARGET_80387 && TARGET_SSE2
! /* Athlon optimizes partial-register FPS special case, thus avoiding the
! need for extra instructions beforehand */
! && TARGET_SSE_PARTIAL_REGS && !TARGET_ATHLON_K8
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
{
switch (which_alternative)
***************
*** 3906,3912 ****
[(set (match_operand:SF 0 "register_operand" "=Y")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
! "!TARGET_80387 && TARGET_SSE2 && !TARGET_SSE_PARTIAL_REGS"
"cvtsd2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
--- 3918,3927 ----
[(set (match_operand:SF 0 "register_operand" "=Y")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
! "!TARGET_80387 && TARGET_SSE2
! /* Athlon optimizes partial-register FPS special case, thus avoiding the
! need for extra instructions beforehand */
! && (!TARGET_SSE_PARTIAL_REGS || TARGET_ATHLON_K8)"
"cvtsd2ss\t{%1, %0|%0, %1}"
[(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
***************
*** 3915,3921 ****
[(set (match_operand:SF 0 "register_operand" "=&Y")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
! "!TARGET_80387 && TARGET_SSE2 && TARGET_SSE_PARTIAL_REGS"
"#"
[(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
--- 3930,3939 ----
[(set (match_operand:SF 0 "register_operand" "=&Y")
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
! "!TARGET_80387 && TARGET_SSE2
! /* Athlon optimizes partial-register FPS special case, thus avoiding the
! need for extra instructions beforehand */
! && TARGET_SSE_PARTIAL_REGS && !TARGET_ATHLON_K8"
"#"
[(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
***************
*** 3942,3948 ****
[(const_int 0)]
{
rtx src, dest;
! if (!TARGET_SSE_PARTIAL_REGS)
emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
else
{
--- 3960,3968 ----
[(const_int 0)]
{
rtx src, dest;
! /* Athlon optimizes partial-register FPS special case, thus avoiding the
! need for extra instructions beforehand */
! if (!TARGET_SSE_PARTIAL_REGS || TARGET_ATHLON_K8)
emit_insn (gen_truncdfsf2_sse_only (operands[0], operands[1]));
else
{
***************
*** 3964,3970 ****
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_80387 && reload_completed
! && SSE_REG_P (operands[0]) && TARGET_SSE_PARTIAL_REGS"
[(const_int 0)]
{
rtx src, dest;
--- 3984,3993 ----
(float_truncate:SF
(match_operand:DF 1 "nonimmediate_operand" "")))]
"TARGET_80387 && reload_completed
! && SSE_REG_P (operands[0])
! /* athlon optimizes partial-register fps special case, thus avoiding the
! need for extra instructions beforehand */
! && TARGET_SSE_PARTIAL_REGS && !TARGET_ATHLON_K8"
[(const_int 0)]
{
rtx src, dest;
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