[patch] h8300: Fix predicates and add insns.
Kazu Hirata
kazu@cs.umass.edu
Tue Nov 12 06:02:00 GMT 2002
Hi,
Attached is a patch to add two insns while fixing predicates
single_one_operand and single_zero_operand when they deal with SImode.
As far as I remember, bit tests like "if (a & 1)" used to become an
insn involving zero_extract. Nowadays, they don't, so the patch
restores the old behavior by adding two new insns.
Tested on h8300. Committed.
Kazu Hirata
2002-11-12 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.c (single_one_operand): Correctly compute
mask when mode is SImode.
(single_zero_operand): Likewise.
* config/h8300/h8300.md (two new anonymous insns): New.
Index: h8300.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.c,v
retrieving revision 1.154
diff -u -r1.154 h8300.c
--- h8300.c 30 Oct 2002 11:21:24 -0000 1.154
+++ h8300.c 12 Nov 2002 13:46:10 -0000
@@ -763,7 +763,9 @@
/* We really need to do this masking because 0x80 in QImode is
represented as -128 for example. */
unsigned HOST_WIDE_INT mask =
- ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
+ (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
+ ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
+ : ~0;
unsigned HOST_WIDE_INT value = INTVAL (operand);
if (exact_log2 (value & mask) >= 0)
@@ -786,7 +788,9 @@
/* We really need to do this masking because 0x80 in QImode is
represented as -128 for example. */
unsigned HOST_WIDE_INT mask =
- ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1;
+ (GET_MODE_BITSIZE (mode) < HOST_BITS_PER_WIDE_INT)
+ ? ((unsigned HOST_WIDE_INT) 1 << GET_MODE_BITSIZE (mode)) - 1
+ : ~0;
unsigned HOST_WIDE_INT value = INTVAL (operand);
if (exact_log2 (~value & mask) >= 0)
Index: h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.98
diff -u -r1.98 h8300.md
--- h8300.md 8 Nov 2002 19:30:31 -0000 1.98
+++ h8300.md 12 Nov 2002 13:46:11 -0000
@@ -599,6 +599,43 @@
[(set_attr "length" "2")
(set_attr "cc" "set_zn")])
+(define_insn ""
+ [(set (cc0)
+ (and:HI (match_operand:HI 0 "register_operand" "r")
+ (match_operand:HI 1 "single_one_operand" "n")))]
+ ""
+ "*
+{
+ operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
+ if (INTVAL (operands[1]) > 128)
+ {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
+ return \"btst\\t%V1,%t0\";
+ }
+ return \"btst\\t%V1,%s0\";
+}"
+ [(set_attr "length" "2")
+ (set_attr "cc" "set_zn")])
+
+(define_insn ""
+ [(set (cc0)
+ (and:SI (match_operand:SI 0 "register_operand" "r")
+ (match_operand:SI 1 "single_one_operand" "n")))]
+ "(TARGET_H8300H || TARGET_H8300S)
+ && (INTVAL (operands[1]) & 0xffff) != 0"
+ "*
+{
+ operands[1] = GEN_INT (INTVAL (operands[1]) & 0xffff);
+ if (INTVAL (operands[1]) > 128)
+ {
+ operands[1] = GEN_INT (INTVAL (operands[1]) >> 8);
+ return \"btst\\t%V1,%x0\";
+ }
+ return \"btst\\t%V1,%w0\";
+}"
+ [(set_attr "length" "2")
+ (set_attr "cc" "set_zn")])
+
(define_insn "tstqi"
[(set (cc0) (match_operand:QI 0 "register_operand" "r"))]
""
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