SSE fixes

Jan Hubicka jh@suse.cz
Sat May 18 06:18:00 GMT 2002


Hi,
the attached patch fixes few conflicts of Bernd's merger and my types patch.

Sat May 18 13:16:45 CEST 2002  Jan Hubicka  <jh@suse.cz>
	* i386.md (movsi/movdi): Fix template.
	(sse2 patterns): Set attributes consistently.

? config/i386/.i386.md.swp
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.361
diff -c -3 -p -r1.361 i386.md
*** config/i386/i386.md	14 May 2002 10:46:27 -0000	1.361
--- config/i386/i386.md	18 May 2002 11:16:04 -0000
***************
*** 1092,1103 ****
  {
    switch (get_attr_type (insn))
      {
!     case TYPE_SSE:
        if (get_attr_mode (insn) == TImode)
          return "movdqa\t{%1, %0|%0, %1}";
        return "movd\t{%1, %0|%0, %1}";
  
!     case TYPE_MMX:
        if (get_attr_mode (insn) == DImode)
  	return "movq\t{%1, %0|%0, %1}";
        return "movd\t{%1, %0|%0, %1}";
--- 1092,1103 ----
  {
    switch (get_attr_type (insn))
      {
!     case TYPE_SSEMOV:
        if (get_attr_mode (insn) == TImode)
          return "movdqa\t{%1, %0|%0, %1}";
        return "movd\t{%1, %0|%0, %1}";
  
!     case TYPE_MMXMOV:
        if (get_attr_mode (insn) == DImode)
  	return "movq\t{%1, %0|%0, %1}";
        return "movd\t{%1, %0|%0, %1}";
***************
*** 1860,1871 ****
  {
    switch (get_attr_type (insn))
      {
!     case TYPE_SSE:
        if (register_operand (operands[0], DImode)
  	  && register_operand (operands[1], DImode))
  	  return "movdqa\t{%1, %0|%0, %1}";
        /* FALLTHRU */
!     case TYPE_MMX:
        return "movq\t{%1, %0|%0, %1}";
      case TYPE_MULTI:
        return "#";
--- 1860,1871 ----
  {
    switch (get_attr_type (insn))
      {
!     case TYPE_SSEMOV:
        if (register_operand (operands[0], DImode)
  	  && register_operand (operands[1], DImode))
  	  return "movdqa\t{%1, %0|%0, %1}";
        /* FALLTHRU */
!     case TYPE_MMXMOV:
        return "movq\t{%1, %0|%0, %1}";
      case TYPE_MULTI:
        return "#";
***************
*** 18026,18032 ****
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "pand\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "*sse_nandti3_df"
    [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18026,18033 ----
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "pand\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sselog")
!    (set_attr "mode" "TI")])
  
  (define_insn "*sse_nandti3_df"
    [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18061,18067 ****
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
    "TARGET_SSE2"
    "pandn\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sselog")])
  
  (define_insn "sse2_nandv2di3"
    [(set (match_operand:V2DI 0 "register_operand" "=x")
--- 18062,18069 ----
  		(match_operand:TI 2 "nonimmediate_operand" "xm")))]
    "TARGET_SSE2"
    "pandn\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sselog")
!    (set_attr "mode" "TI")])
  
  (define_insn "sse2_nandv2di3"
    [(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 18070,18076 ****
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "pandn\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "*sse_iorti3_df_1"
    [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18072,18079 ----
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "pandn\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sselog")
!    (set_attr "mode" "TI")])
  
  (define_insn "*sse_iorti3_df_1"
    [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18135,18141 ****
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "por\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "*sse_xorti3_df_1"
    [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18138,18145 ----
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "por\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sselog")
!    (set_attr "mode" "TI")])
  
  (define_insn "*sse_xorti3_df_1"
    [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18200,18206 ****
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "pxor\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  ;; Use xor, but don't show input operands so they aren't live before
  ;; this insn.
--- 18204,18211 ----
    "TARGET_SSE2
     && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
    "pxor\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sselog")
!    (set_attr "mode" "TI")])
  
  ;; Use xor, but don't show input operands so they aren't live before
  ;; this insn.
***************
*** 20602,20608 ****
  		     (match_operand:SI 2 "nonmemory_operand" "ri")))]
    "TARGET_SSE2"
    "pslld\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "ashlv2di3"
    [(set (match_operand:V2DI 0 "register_operand" "=x")
--- 20607,20614 ----
  		     (match_operand:SI 2 "nonmemory_operand" "ri")))]
    "TARGET_SSE2"
    "pslld\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "ashlv2di3"
    [(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20610,20616 ****
  		     (match_operand:SI 2 "nonmemory_operand" "ri")))]
    "TARGET_SSE2"
    "psllq\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "ashrv8hi3_ti"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20616,20623 ----
  		     (match_operand:SI 2 "nonmemory_operand" "ri")))]
    "TARGET_SSE2"
    "psllq\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "ashrv8hi3_ti"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20618,20624 ****
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psraw\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "ashrv4si3_ti"
    [(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20625,20632 ----
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psraw\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "ashrv4si3_ti"
    [(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20626,20632 ****
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrad\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "lshrv8hi3_ti"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20634,20641 ----
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrad\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "lshrv8hi3_ti"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20634,20640 ****
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrlw\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "lshrv4si3_ti"
    [(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20643,20650 ----
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrlw\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "lshrv4si3_ti"
    [(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 20642,20648 ****
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrld\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "lshrv2di3_ti"
    [(set (match_operand:V2DI 0 "register_operand" "=x")
--- 20652,20659 ----
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrld\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "lshrv2di3_ti"
    [(set (match_operand:V2DI 0 "register_operand" "=x")
***************
*** 20650,20656 ****
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrlq\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "ashlv8hi3_ti"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
--- 20661,20668 ----
  		       (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psrlq\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "ashlv8hi3_ti"
    [(set (match_operand:V8HI 0 "register_operand" "=x")
***************
*** 20658,20664 ****
  		     (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psllw\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sse")])
  
  (define_insn "ashlv4si3_ti"
    [(set (match_operand:V4SI 0 "register_operand" "=x")
--- 20670,20677 ----
  		     (subreg:TI (match_operand:V2DI 2 "nonmemory_operand" "xi") 0)))]
    "TARGET_SSE2"
    "psllw\t{%2, %0|%0, %2}"
!   [(set_attr "type" "sseishft")
!    (set_attr "mode" "TI")])
  
  (define_insn "ashlv4si3_ti"
    [(set (match_operand:V4SI 0 "register_operand" "=x")



More information about the Gcc-patches mailing list