gcc-64 on HP-UX 11.00

[John David Anglin]

>  > Why a GPR?  We need the result in a FPR for xmpyu.
> You need FPRs for the inputs/outputs of xmpyu, but if one of the inputs is
> something like a MEM, then you have a secondary reload situation where we
> allocate a GPR as a scratch (for example for holding the address of the MEM).

But in this case, we don't need the address of the MEM.  The pattern at
line 2234 in pa.md can handle the secondary reload of the MEM (2nd last
alternative) if we change the T constraint to allow non-pic LO_SUMs.
This allows the MEM to get directly loaded into the FPR for the xmpyu.
Isn't it just the pic case that the pattern can't handle?

I enclose below my current fixes for the pa-risc-2-0 boot problems.
GAS doesn't understand "be,l"!  The two "xmpyu" patterns with operand 2
"uint32_operand" seem suspect to me.  They will need a reload so
maybe they should be deleted.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6605)

--- pa.c.save	Fri May 17 08:33:56 2002
+++ pa.c	Fri May 17 13:35:39 2002
@@ -6085,13 +6085,13 @@ output_millicode_call (insn, call_dest)
 	     executed once.  To be safe we use a nop.  */
 	  output_asm_insn ("nop", xoperands);
 	}
-      /* If we're allowed to use be/ble instructions, then this is the
+      /* If we're allowed to use ble (be,l) instructions, then this is the
 	 best sequence to use for a long millicode call.  */
       else
 	{
 	  xoperands[0] = call_dest;
 	  output_asm_insn ("ldil L%%%0,%3", xoperands);
-	  output_asm_insn ("{ble|be,l} R%%%0(%%sr4,%3)", xoperands);
+	  output_asm_insn ("ble R%%%0(%%sr4,%3)", xoperands);
 	  output_asm_insn ("nop", xoperands);
 	}
 
@@ -6347,7 +6347,7 @@ output_call (insn, call_dest, sibcall)
 	      /* Get the high part of the  address of $dyncall into %r2, then
 		 add in the low part in the branch instruction.  */
 	      output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
-	      output_asm_insn ("{ble|be,l}  R%%$$dyncall(%%sr4,%%r2)",
+	      output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)",
 			       xoperands);
 
 	      if (sibcall)
--- pa.h.save	Fri May 17 08:33:57 2002
+++ pa.h	Fri May 17 10:56:22 2002
@@ -1243,7 +1243,9 @@ extern int may_call_alloca;
 			     ? GET_MODE (OP)		\
 			     : DFmode),			\
 			    XEXP (OP, 0))		\
-       && GET_CODE (XEXP (OP, 0)) != LO_SUM		\
+       && !(GET_CODE (XEXP (OP, 0)) == LO_SUM		\
+	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG	\
+	    && GET_CODE (XEXP (XEXP (OP, 0), 1)) == UNSPEC)\
        && !(GET_CODE (XEXP (OP, 0)) == PLUS		\
 	    && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
 		|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)))\
--- pa.md.orig	Fri May 17 13:30:05 2002
+++ pa.md	Fri May 17 13:31:20 2002
@@ -4042,17 +4042,17 @@
 }")
 
 (define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
-		 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
+  [(set (match_operand:DI 0 "register_operand" "=f")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
+		 (zero_extend:DI (match_operand:SI 2 "register_operand" "f"))))]
   "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
   "xmpyu %1,%2,%0"
   [(set_attr "type" "fpmuldbl")
    (set_attr "length" "4")])
 
 (define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
+  [(set (match_operand:DI 0 "register_operand" "=f")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
 		 (match_operand:DI 2 "uint32_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
   "xmpyu %1,%R2,%0"
@@ -4060,8 +4060,8 @@
    (set_attr "length" "4")])
 
 (define_insn ""
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
-	(mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
+  [(set (match_operand:DI 0 "register_operand" "=f")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "f"))
 		 (match_operand:DI 2 "uint32_operand" "f")))]
   "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
   "xmpyu %1,%2R,%0"