altivec: m*vscr volatile

[Aldy Hernandez]

hello.

mtvscr operations are being wrongly moved by the scheduler, because
gcc doesn't know that VSCR is affected by pretty much every
altivec operation.

ok for mainline?

2002-05-06  Aldy Hernandez  <aldyh@redhat.com>

	* config/rs6000/rs6000.md ("altivec_mtvscr"): Change to
	unspec_volatile.
	("altivec_mfvscr"): Same.

Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.182
diff -c -p -r1.182 rs6000.md
*** config/rs6000/rs6000.md	28 Apr 2002 20:26:54 -0000	1.182
--- config/rs6000/rs6000.md	6 May 2002 05:40:37 -0000
***************
*** 15500,15513 ****
  [(set_attr "type" "veccmp")])
  
  (define_insn "altivec_mtvscr"
!   [(unspec [(match_operand:V4SI 0 "register_operand" "v")] 186)]
    "TARGET_ALTIVEC"
    "mtvscr %0"
    [(set_attr "type" "vecsimple")])
  
  (define_insn "altivec_mfvscr"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
! 	(unspec:V8HI [(const_int 0)] 187))]
    "TARGET_ALTIVEC"
    "mfvscr %0"
    [(set_attr "type" "vecsimple")])
--- 15500,15513 ----
  [(set_attr "type" "veccmp")])
  
  (define_insn "altivec_mtvscr"
!   [(unspec_volatile [(match_operand:V4SI 0 "register_operand" "v")] 186)]
    "TARGET_ALTIVEC"
    "mtvscr %0"
    [(set_attr "type" "vecsimple")])
  
  (define_insn "altivec_mfvscr"
    [(set (match_operand:V8HI 0 "register_operand" "=v")
! 	(unspec_volatile:V8HI [(const_int 0)] 187))]
    "TARGET_ALTIVEC"
    "mfvscr %0"
    [(set_attr "type" "vecsimple")])