Patch to decrease time of building minimal delay issue table for the DFA scheduler
Vladimir Makarov
vmakarov@redhat.com
Fri May 3 14:17:00 GMT 2002
The following patch considerably (in 10 or more times) descreases
time of building minimal issue delay table for the DFA scheduler for
some cases.
I've commited it into the main line.
Vlad
2002-05-03 Vladimir Makarov <vmakarov@redhat.com>
* genautomata.c (min_issue_delay_pass_states): Change return
type
in the prototype.
(min_issue_delay_pass_states): Change the algorithm.
(min_issue_delay): Set up min_insn_issue_delay for the state.
(output_min_issue_delay_table): Interchange the nested loops and
and initiate min_insn_issue_delay for states.
Index: genautomata.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/genautomata.c,v
retrieving revision 1.5
diff -c -p -r1.5 genautomata.c
*** genautomata.c 2 May 2002 13:55:33 -0000 1.5
--- genautomata.c 3 May 2002 21:08:41 -0000
***************
*** 1,5 ****
/* Pipeline hazard description translator.
! Copyright (C) 2000, 2001 Free Software Foundation, Inc.
Written by Vladimir Makarov <vmakarov@redhat.com>
--- 1,5 ----
/* Pipeline hazard description translator.
! Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
Written by Vladimir Makarov <vmakarov@redhat.com>
*************** static void add_vect_el PARAMS
*** 448,454 ****
static void add_states_vect_el PARAMS ((state_t));
static void output_trans_table PARAMS ((automaton_t));
static void output_state_alts_table PARAMS ((automaton_t));
! static void min_issue_delay_pass_states PARAMS ((state_t, ainsn_t));
static int min_issue_delay PARAMS ((state_t, ainsn_t));
static void initiate_min_issue_delay_pass_states PARAMS ((void));
static void output_min_issue_delay_table PARAMS ((automaton_t));
--- 448,454 ----
static void add_states_vect_el PARAMS ((state_t));
static void output_trans_table PARAMS ((automaton_t));
static void output_state_alts_table PARAMS ((automaton_t));
! static int min_issue_delay_pass_states PARAMS ((state_t, ainsn_t));
static int min_issue_delay PARAMS ((state_t, ainsn_t));
static void initiate_min_issue_delay_pass_states PARAMS ((void));
static void output_min_issue_delay_table PARAMS ((automaton_t));
*************** static int curr_state_pass_num;
*** 7114,7121 ****
/* This recursive function passes states to find minimal issue delay
! value for AINSN. The state being visited is STATE. */
! static void
min_issue_delay_pass_states (state, ainsn)
state_t state;
ainsn_t ainsn;
--- 7114,7123 ----
/* This recursive function passes states to find minimal issue delay
! value for AINSN. The state being visited is STATE. The function
! returns minimal issue delay value for AINSN in STATE or -1 if we
! enter into a loop. */
! static int
min_issue_delay_pass_states (state, ainsn)
state_t state;
ainsn_t ainsn;
*************** min_issue_delay_pass_states (state, ains
*** 7123,7132 ****
arc_t arc;
int min_insn_issue_delay, insn_issue_delay;
! if (state->state_pass_num == curr_state_pass_num)
! return;
state->state_pass_num = curr_state_pass_num;
! min_insn_issue_delay = state->min_insn_issue_delay = -1;
for (arc = first_out_arc (state); arc != NULL; arc = next_out_arc
(arc))
if (arc->insn == ainsn)
{
--- 7125,7137 ----
arc_t arc;
int min_insn_issue_delay, insn_issue_delay;
! if (state->state_pass_num == curr_state_pass_num
! || state->min_insn_issue_delay != -1)
! /* We've entered into a loop or already have the correct value for
! given state and ainsn. */
! return state->min_insn_issue_delay;
state->state_pass_num = curr_state_pass_num;
! min_insn_issue_delay = -1;
for (arc = first_out_arc (state); arc != NULL; arc = next_out_arc
(arc))
if (arc->insn == ainsn)
{
*************** min_issue_delay_pass_states (state, ains
*** 7135,7165 ****
}
else
{
! min_issue_delay_pass_states (arc->to_state, ainsn);
! if (arc->to_state->min_insn_issue_delay != -1)
{
! insn_issue_delay
! = (arc->to_state->min_insn_issue_delay
! + (arc->insn->insn_reserv_decl
! == &advance_cycle_insn_decl->decl.insn_reserv ? 1 :
0));
if (min_insn_issue_delay == -1
|| min_insn_issue_delay > insn_issue_delay)
! min_insn_issue_delay = insn_issue_delay;
}
}
! state->min_insn_issue_delay = min_insn_issue_delay;
}
/* The function searches minimal issue delay value for AINSN in STATE.
! The function can return negative can not issue AINSN. We will
! report about it later. */
static int
min_issue_delay (state, ainsn)
state_t state;
ainsn_t ainsn;
{
curr_state_pass_num++;
! min_issue_delay_pass_states (state, ainsn);
return state->min_insn_issue_delay;
}
--- 7140,7173 ----
}
else
{
! insn_issue_delay = min_issue_delay_pass_states (arc->to_state,
ainsn);
! if (insn_issue_delay != -1)
{
! if (arc->insn->insn_reserv_decl
! == &advance_cycle_insn_decl->decl.insn_reserv)
! insn_issue_delay++;
if (min_insn_issue_delay == -1
|| min_insn_issue_delay > insn_issue_delay)
! {
! min_insn_issue_delay = insn_issue_delay;
! if (insn_issue_delay == 0)
! break;
! }
}
}
! return min_insn_issue_delay;
}
/* The function searches minimal issue delay value for AINSN in STATE.
! The function can return negative value if we can not issue AINSN.
We
! will report about it later. */
static int
min_issue_delay (state, ainsn)
state_t state;
ainsn_t ainsn;
{
curr_state_pass_num++;
! state->min_insn_issue_delay = min_issue_delay_pass_states (state,
ainsn);
return state->min_insn_issue_delay;
}
*************** output_min_issue_delay_table (automaton)
*** 7199,7213 ****
i++)
VLA_HWINT (min_issue_delay_vect, i) = 0;
automaton->max_min_delay = 0;
! for (state_ptr = VLA_PTR_BEGIN (output_states_vect);
! state_ptr <= (state_t *) VLA_PTR_LAST (output_states_vect);
! state_ptr++)
! {
! for (ainsn = automaton->ainsn_list;
! ainsn != NULL;
! ainsn = ainsn->next_ainsn)
! if (ainsn->first_ainsn_with_given_equialence_num)
! {
min_delay = min_issue_delay (*state_ptr, ainsn);
if (automaton->max_min_delay < min_delay)
automaton->max_min_delay = min_delay;
--- 7207,7223 ----
i++)
VLA_HWINT (min_issue_delay_vect, i) = 0;
automaton->max_min_delay = 0;
! for (ainsn = automaton->ainsn_list; ainsn != NULL; ainsn =
ainsn->next_ainsn)
! if (ainsn->first_ainsn_with_given_equialence_num)
! {
! for (state_ptr = VLA_PTR_BEGIN (output_states_vect);
! state_ptr <= (state_t *) VLA_PTR_LAST (output_states_vect);
! state_ptr++)
! (*state_ptr)->min_insn_issue_delay = -1;
! for (state_ptr = VLA_PTR_BEGIN (output_states_vect);
! state_ptr <= (state_t *) VLA_PTR_LAST (output_states_vect);
! state_ptr++)
! {
min_delay = min_issue_delay (*state_ptr, ainsn);
if (automaton->max_min_delay < min_delay)
automaton->max_min_delay = min_delay;
*************** output_min_issue_delay_table (automaton)
*** 7216,7222 ****
* automaton->insn_equiv_classes_num
+ ainsn->insn_equiv_class_num) = min_delay;
}
! }
fprintf (output_file, "/* Vector of min issue delay of insns.*/\n");
fprintf (output_file, "static const ");
output_range_type (output_file, 0, automaton->max_min_delay);
--- 7226,7232 ----
* automaton->insn_equiv_classes_num
+ ainsn->insn_equiv_class_num) = min_delay;
}
! }
fprintf (output_file, "/* Vector of min issue delay of insns.*/\n");
fprintf (output_file, "static const ");
output_range_type (output_file, 0, automaton->max_min_delay);
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