minor alpha corrections

Richard Henderson rth@redhat.com
Mon Jun 10 14:06:00 GMT 2002


Two problems noticed by Falk Hueffner in private mail.


r~


        * config/alpha/alpha.md (builtin_zap): Fix thinkos expanding mask.
        (builtin_zapnot): Likewise.

        * config/alpha/ev5.md: Don't combine shift and mvi insns in one
        reservation.

Index: config/alpha/alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.191
diff -c -p -d -u -r1.191 alpha.md
--- config/alpha/alpha.md	4 Jun 2002 22:45:51 -0000	1.191
+++ config/alpha/alpha.md	10 Jun 2002 21:01:10 -0000
@@ -7301,12 +7301,12 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
     {
       rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
 
-      if (operands[1] == const0_rtx)
+      if (mask == const0_rtx)
 	{
 	  emit_move_insn (operands[0], const0_rtx);
 	  DONE;
 	}
-      if (operands[1] == constm1_rtx)
+      if (mask == constm1_rtx)
 	{
 	  emit_move_insn (operands[0], operands[1]);
 	  DONE;
@@ -7394,12 +7394,12 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
     {
       rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
 
-      if (operands[1] == const0_rtx)
+      if (mask == const0_rtx)
 	{
 	  emit_move_insn (operands[0], const0_rtx);
 	  DONE;
 	}
-      if (operands[1] == constm1_rtx)
+      if (mask == constm1_rtx)
 	{
 	  emit_move_insn (operands[0], operands[1]);
 	  DONE;
Index: config/alpha/ev5.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/ev5.md,v
retrieving revision 1.1
diff -c -p -d -u -r1.1 ev5.md
--- config/alpha/ev5.md	5 May 2002 21:54:39 -0000	1.1
+++ config/alpha/ev5.md	10 Jun 2002 21:01:10 -0000
@@ -64,9 +64,14 @@
        (eq_attr "type" "jsr"))
   "ev5_e1")
 
-(define_insn_reservation "ev5_shiftmvi" 2
+(define_insn_reservation "ev5_shift" 1
   (and (eq_attr "cpu" "ev5")
-       (eq_attr "type" "shift,mvi"))
+       (eq_attr "type" "shift"))
+  "ev5_e0")
+
+(define_insn_reservation "ev5_mvi" 2
+  (and (eq_attr "cpu" "ev5")
+       (eq_attr "type" "mvi"))
   "ev5_e0")
 
 (define_insn_reservation "ev5_cmov" 2
@@ -119,7 +124,7 @@
 ; Model this instead with increased latency on the input instruction.
 
 (define_bypass 3
-  "ev5_ld,ev5_shiftmvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
+  "ev5_ld,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp"
   "ev5_imull,ev5_imulq,ev5_imulh")
 
 (define_bypass  9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh")



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