AIX regression due to DFA scheduler merge

Vladimir N. Makarov vmakarov@redhat.com
Sun Jun 2 10:25:00 GMT 2002


David Edelsohn wrote:

>         I have tracked down the miscompilation and it looks like the
> scheduler with the libcall patch is ignoring a REG_DEP_ANTI note, but I do
> not understand why.
>
>         The incorrect scheduling visible in the PowerPC assembly code is:
>
>         li 27,0
> L..68:
>         add 4,4,26
>         mr 3,24
>         add 27,27,22    <*** increment r27
>         bl .gen_rtx_REG
>         nop
>         addi 26,26,1
>         lwz 0,40(30)
>         mr 10,0
>         srawi 9,0,31
>         mr 12,27        <*** copy r27 (should be old value)
>         srawi 11,27,31  <*** shift r27 (should be old value)
>         addc 5,10,12
>         adde 4,9,11
>
> L..68 is the label for a loop and r27 is a loop counter.  If the r27 loop
> variable increment is moved after the copy and shift uses (where it was
> before scheduling, the compiler works correctly.
>
>         Prior to the first scheduling pass, the RTL fragment from the end
> of the loop where the loop counter increment occurs is below.  reg:SI 791
> will become r27 and reg:SI 122 will become r22.
>
> (note 1788 1787 1790 3055fdc0 NOTE_INSN_BLOCK_END)
>
> (note 1790 1788 2951 NOTE_INSN_LOOP_CONT)
>
> (insn 2951 1790 1793 (set (reg:SI 791)
>         (plus:SI (reg:SI 791)
>             (reg/v:SI 122))) 36 {*addsi3_internal1} (nil)
>     (nil))
>
> (insn 1793 2951 1794 (set (reg/v:SI 492)
>         (plus:SI (reg/v:SI 492)
>             (const_int 1 [0x1]))) 36 {*addsi3_internal1} (nil)
>     (nil))
>
> (jump_insn 1794 1793 1795 (set (pc)
>         (label_ref 1661)) 509 {jump} (nil)
>     (nil))
> ;; End of basic block 45, registers live:
>  1 [1] 2 [2] 31 [31] 67 [ap] 116 117 122 127 133 140 492 509 791
>
> After scheduling *with* the libcall patch, the relevant portion of RTL is:
>
> (insn 2951 3107 3108 (set (reg:SI 791)
>         (plus:SI (reg:SI 791)
>             (reg/v:SI 122))) 36 {*addsi3_internal1}
>         (insn_list:REG_DEP_ANTI 1711  (insn_list:REG_DEP_ANTI 1715 (nil)))
>     (nil))
>
> ...
>
> (insn 1711 1716 1715 (set (subreg:SI (reg:DI 506) 4)
>         (reg:SI 791)) 305 {*movsi_internal1} (insn_list:REG_DEP_ANTI 1692 (nil))
>     (expr_list:REG_NO_CONFLICT (reg:SI 791)
>         (nil)))
>
> (insn 1715 1711 1718 (set (subreg:SI (reg:DI 506) 0)
>         (ashiftrt:SI (reg:SI 791)
>             (const_int 31 [0x1f]))) 162 {ashrsi3_no_power} (insn_list:REG_DEP_ANTI 1692 (nil))
>     (expr_list:REG_NO_CONFLICT (reg:SI 791)
>         (nil)))
>
> (insn 1718 1715 1695 (set (reg:DI 506)
>         (reg:DI 506)) 328 {*movdi_internal32} (insn_list:REG_DEP_ANTI 1692 (nil))
>     (insn_list:REG_RETVAL 1716 (expr_list:REG_EQUAL (sign_extend:DI (reg:SI 791))
>             (nil))))
>
> *Without* the libcall patch, the RTL is:
>
> (insn 1711 1695 1715 (set (subreg:SI (reg:DI 506) 4)
>         (reg:SI 791)) 296 {*movsi_internal1} (insn_list:REG_DEP_OUTPUT 1716 (insn_list:REG_DEP_ANTI 1692 (nil)))
>     (expr_list:REG_NO_CONFLICT (reg:SI 791)
>         (nil)))
>
> (insn 1715 1711 1718 (set (subreg:SI (reg:DI 506) 0)
>         (ashiftrt:SI (reg:SI 791)
>             (const_int 31 [0x1f]))) 153 {ashrsi3_no_power} (insn_list:REG_DEP_OUTPUT 1711 (insn_list:REG_DEP_ANTI 1692 (nil)))
>     (expr_list:REG_NO_CONFLICT (reg:SI 791)
>         (nil)))
>
> (insn 1718 1715 3110 (set (reg:DI 506)
>         (reg:DI 506)) 319 {*movdi_internal32} (insn_list 1715 (insn_list:REG_DEP_ANTI 1692 (nil)))
>     (insn_list:REG_RETVAL 1716 (expr_list:REG_EQUAL (sign_extend:DI (reg:SI 791))
>             (nil))))
>
> (note 3110 1718 2954 30121600 NOTE_INSN_BLOCK_END)
>
> (insn 2954 3110 3111 (set (reg:SI 791)
>         (plus:SI (reg:SI 791)
>             (reg/v:SI 122))) 36 {*addsi3_internal1} (insn_list:REG_DEP_ANTI 1711 (insn_list:REG_DEP_ANTI 1715 (nil)))
>     (nil))
>
> With the libcall patch, insn 2951 (plus:SI) is scheduled before insn 1711
> and insn 1715 on which it has anti-dependence.  Without the libcall patch,
> it is scheduled after those instructions where reg:SI 791 is used.
>
>         I would really appreciate some help debugging why the instruction
> is being moved across the dependency.  I will be happy to send
> pre-processed input and any RTL dumps people want to browse.

  You can send it to me.  I'll look at this tomorrow.  And please, some instructions how to reproduce it.  The scheduler uses
forward dependencies in its work.  RTL contains only backward dependencies.  To get forward dependencies, please use
-fsched-verbose=5.

  I have suspicion that there is some conflict in setting SCHED_GROUP_P for libcalls (your patch) and calls (it is present in
sources long ago) because calls can be inside libcalls.


Vlad





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