Optimize C / R.

Jan Hubicka jh@suse.cz
Sat Jul 20 15:42:00 GMT 2002


> 
> The x86 backend could still implement the above RTL with a load from
> the constant pool.  The important thing is keeping the const0_rtx
> explicit in the RTL representation.  This can then be optimized away
> by GCC in most of its uses.  Having the RTL record this as a load from
> mem, hides the nature of the constant and the potential aliasing of
> that MEM could adversely affect even more optimizations.

This should more or less work with constant references as well.
Simlify-rtx and friends usually contains code to lookup the value in
constant pool when necesary.
> 
> For example, because "fldz" is independent of all other x86 instructions,
> it can often be moved past other instructions (in reg-stack.c?) and
> scheduled next to its use (with As-Late-As-Possible scheduling).  This
> would avoid any fstp.  And as you know, "fxch" is free on current
> generation processors.  If all else fails a "movsf_zero" pattern could

It is not the case for pentiumpro and newer.  On most modern chips it
counts as separate instruction unforutnately.

I will try to check in detail what is going on.  I've just returned from
meeting and leaving for another vacation soonish so my time is limited
right now, but in worst case I will definitly do after returning (at
9th)

Honza
> just load from the constant pool.  Indeed on processors where this
> is faster than "fldz" (athlon?), this mechansim provides the tuning
> opportunity to do that.
> 
> > We may want to re-benchmark it or figure out better solution...
> 
> Unfortunately, implementing a "movsf_zero" pattern is beyond my current
> skills or I'd try some timings myself (and send a polite e-mail to
> Andreas).
> 
> Roger
> --



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