[alpha] divide patterns vs plt

[Richard Henderson]

Generate more lituse_jsr relocs.  This time we make the divide
patterns use the plt again.


r~


        * config/alpha/alpha.md (divmodsi_internal_er): Generate lituse
        sequence number for the literal.
        (divmoddi_internal_er): Likewise.

Index: alpha.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/alpha/alpha.md,v
retrieving revision 1.175
diff -c -p -d -r1.175 alpha.md
*** alpha.md	2002/01/11 03:47:24	1.175
--- alpha.md	2002/01/22 23:10:58
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1212,1217 ****
--- 1212,1218 ----
    [(parallel [(set (match_dup 0)
  		   (sign_extend:DI (match_dup 3)))
  	      (use (match_dup 0))
+ 	      (use (match_dup 4))
  	      (clobber (reg:DI 23))
  	      (clobber (reg:DI 28))])]
  {
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1233,1239 ****
      default:
        abort ();
      }
!   emit_move_insn (operands[0], gen_rtx_SYMBOL_REF (DImode, str));
  }
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
--- 1234,1243 ----
      default:
        abort ();
      }
!   operands[4] = GEN_INT (alpha_next_sequence_number++);
!   emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
! 				  gen_rtx_SYMBOL_REF (DImode, str),
! 				  operands[4]));
  }
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1244,1253 ****
                          [(match_operand:DI 1 "register_operand" "a")
                           (match_operand:DI 2 "register_operand" "b")])))
     (use (match_operand:DI 4 "register_operand" "c"))
     (clobber (reg:DI 23))
     (clobber (reg:DI 28))]
    "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
!   "jsr $23,($27),__%E3"
    [(set_attr "type" "jsr")
     (set_attr "length" "4")])
  
--- 1248,1258 ----
                          [(match_operand:DI 1 "register_operand" "a")
                           (match_operand:DI 2 "register_operand" "b")])))
     (use (match_operand:DI 4 "register_operand" "c"))
+    (use (match_operand 5 "const_int_operand" ""))
     (clobber (reg:DI 23))
     (clobber (reg:DI 28))]
    "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
!   "jsr $23,($27),__%E3%J5"
    [(set_attr "type" "jsr")
     (set_attr "length" "4")])
  
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1275,1280 ****
--- 1280,1286 ----
    "&& reload_completed"
    [(parallel [(set (match_dup 0) (match_dup 3))
  	      (use (match_dup 0))
+ 	      (use (match_dup 4))
  	      (clobber (reg:DI 23))
  	      (clobber (reg:DI 28))])]
  {
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1296,1302 ****
      default:
        abort ();
      }
!   emit_move_insn (operands[0], gen_rtx_SYMBOL_REF (DImode, str));
  }
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
--- 1302,1311 ----
      default:
        abort ();
      }
!   operands[4] = GEN_INT (alpha_next_sequence_number++);
!   emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
! 				  gen_rtx_SYMBOL_REF (DImode, str),
! 				  operands[4]));
  }
    [(set_attr "type" "jsr")
     (set_attr "length" "8")])
*************** fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi
*** 1307,1316 ****
                          [(match_operand:DI 1 "register_operand" "a")
                           (match_operand:DI 2 "register_operand" "b")]))
     (use (match_operand:DI 4 "register_operand" "c"))
     (clobber (reg:DI 23))
     (clobber (reg:DI 28))]
    "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
!   "jsr $23,($27),__%E3"
    [(set_attr "type" "jsr")
     (set_attr "length" "4")])
  
--- 1316,1326 ----
                          [(match_operand:DI 1 "register_operand" "a")
                           (match_operand:DI 2 "register_operand" "b")]))
     (use (match_operand:DI 4 "register_operand" "c"))
+    (use (match_operand 5 "const_int_operand" ""))
     (clobber (reg:DI 23))
     (clobber (reg:DI 28))]
    "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
!   "jsr $23,($27),__%E3%J5"
    [(set_attr "type" "jsr")
     (set_attr "length" "4")])