Add minimal traceback table and prefetch to rs6000.

[David Edelsohn]

>>>>> Dale Johannesen writes:

Dale> Of course in this case the macros can check for the mode.

	Yes, exactly.  It knows that this is for a Vector mode MEM to tag
all of those instructions.  There is no way to tag these addresses.

	My two thoughts were to add an extra constraint which could prompt
legitimize_reload_address() to force both operands into regs (as is done
for ALTIVEC_VECTOR_MODE), or some phase transition between the patterns to
generate the initial prefetch RTL and then re-recognize it or massage it
into the allowed post-reload RTL.

David