altivec: memory vector moves from GPRs
Aldy Hernandez
aldyh@redhat.com
Tue Feb 12 01:41:00 GMT 2002
the vector initializer code has triggered a memory load of V4SI (et al)
from GPRs. i'll spare everyone the nasty details, but it's for things
like:
vector int foo = (vector int) { bar(), 32, i+3, j };
here is a patch to:
a) tighten the predicate for the lvx and stvx instructions
which were being called incorrectly.
b) add an alternative for loading into memory from gprs
(for v4si, v8hi, v16qi, v4sf).
this will simplify a bit of the vector initializer code which was
incorrect. i will resubmit the vector init patch shortly.
ok?
2002-02-12 Aldy Hernandez <aldyh@redhat.com>
* rs6000.md: Use predicate altivec_register_operand for
altivec_lvx* and altivec_stvx*.
("*movv4si_internal"): Add constraint for loading from GPRs.
("*movv8hi_internal1"): Same.
("*movv16qi_internal1"): Same.
("*movv4sf_internal1"): Same.
* rs6000.c (altivec_register_operand): New.
* rs6000.h (PREDICATE_CODES): Add altivec_register_operand.
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.283
diff -c -p -r1.283 rs6000.c
*** rs6000.c 2002/02/11 06:15:35 1.283
--- rs6000.c 2002/02/12 06:10:05
*************** count_register_operand (op, mode)
*** 710,715 ****
--- 710,726 ----
return 0;
}
+ /* Returns 1 if op is an altivec register. */
+ int
+ altivec_register_operand (op, mode)
+ rtx op;
+ enum machine_mode mode ATTRIBUTE_UNUSED;
+ {
+ return (GET_CODE (op) == REG
+ && (REGNO (op) > FIRST_PSEUDO_REGISTER
+ || ALTIVEC_REGNO_P (REGNO (op))));
+ }
+
int
xer_operand (op, mode)
rtx op;
Index: config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.179
diff -c -p -r1.179 rs6000.h
*** rs6000.h 2002/02/11 06:15:36 1.179
--- rs6000.h 2002/02/12 06:10:07
*************** extern char rs6000_reg_names[][8]; /* re
*** 2762,2767 ****
--- 2762,2768 ----
GT, LEU, LTU, GEU, GTU}}, \
{"boolean_operator", {AND, IOR, XOR}}, \
{"boolean_or_operator", {IOR, XOR}}, \
+ {"altivec_register_operand", {REG}}, \
{"min_max_operator", {SMIN, SMAX, UMIN, UMAX}},
/* uncomment for disabling the corresponding default options */
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.165
diff -c -p -r1.165 rs6000.md
*** rs6000.md 2002/02/11 06:15:37 1.165
--- rs6000.md 2002/02/12 06:10:16
***************
*** 13871,13898 ****
;; Generic LVX load instruction.
(define_insn "altivec_lvx_4si"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
(match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvx_8hi"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
(match_operand:V8HI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvx_16qi"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
(match_operand:V16QI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvx_4sf"
! [(set (match_operand:V4SF 0 "register_operand" "=v")
(match_operand:V4SF 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
--- 13871,13898 ----
;; Generic LVX load instruction.
(define_insn "altivec_lvx_4si"
! [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
(match_operand:V4SI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvx_8hi"
! [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
(match_operand:V8HI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvx_16qi"
! [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
(match_operand:V16QI 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvx_4sf"
! [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
(match_operand:V4SF 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
***************
*** 13901,13928 ****
;; Generic STVX store instruction.
(define_insn "altivec_stvx_4si"
[(set (match_operand:V4SI 0 "memory_operand" "=m")
! (match_operand:V4SI 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvx_8hi"
[(set (match_operand:V8HI 0 "memory_operand" "=m")
! (match_operand:V8HI 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvx_16qi"
[(set (match_operand:V16QI 0 "memory_operand" "=m")
! (match_operand:V16QI 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvx_4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
! (match_operand:V4SF 1 "register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
--- 13901,13928 ----
;; Generic STVX store instruction.
(define_insn "altivec_stvx_4si"
[(set (match_operand:V4SI 0 "memory_operand" "=m")
! (match_operand:V4SI 1 "altivec_register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvx_8hi"
[(set (match_operand:V8HI 0 "memory_operand" "=m")
! (match_operand:V8HI 1 "altivec_register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvx_16qi"
[(set (match_operand:V16QI 0 "memory_operand" "=m")
! (match_operand:V16QI 1 "altivec_register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
(define_insn "altivec_stvx_4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
! (match_operand:V4SF 1 "altivec_register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
***************
*** 13935,13949 ****
"{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
(define_insn "*movv4si_internal"
! [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v")
! (match_operand:V4SI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1"
! [(set_attr "type" "altivec")])
(define_expand "movv8hi"
[(set (match_operand:V8HI 0 "nonimmediate_operand" "")
(match_operand:V8HI 1 "any_operand" ""))]
--- 13935,13952 ----
"{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
(define_insn "*movv4si_internal"
! [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,m")
! (match_operand:V4SI 1 "input_operand" "v,m,v,r"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1
! {st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0"
+ [(set_attr "type" "altivec")
+ (set_attr "length" "*,*,*,16")])
+
(define_expand "movv8hi"
[(set (match_operand:V8HI 0 "nonimmediate_operand" "")
(match_operand:V8HI 1 "any_operand" ""))]
***************
*** 13951,13964 ****
"{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
(define_insn "*movv8hi_internal1"
! [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v")
! (match_operand:V8HI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1"
! [(set_attr "type" "altivec")])
(define_expand "movv16qi"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
--- 13954,13969 ----
"{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
(define_insn "*movv8hi_internal1"
! [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,m")
! (match_operand:V8HI 1 "input_operand" "v,m,v,r"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1
! {st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0"
! [(set_attr "type" "altivec")
! (set_attr "length" "*,*,*,16")])
(define_expand "movv16qi"
[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
***************
*** 13967,13980 ****
"{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
(define_insn "*movv16qi_internal1"
! [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v")
! (match_operand:V16QI 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1"
! [(set_attr "type" "altivec")])
(define_expand "movv4sf"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
--- 13972,13987 ----
"{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
(define_insn "*movv16qi_internal1"
! [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,m")
! (match_operand:V16QI 1 "input_operand" "v,m,v,r"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1
! {st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0"
! [(set_attr "type" "altivec")
! (set_attr "length" "*,*,*,16")])
(define_expand "movv4sf"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
***************
*** 13983,13996 ****
"{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
(define_insn "*movv4sf_internal1"
! [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v")
! (match_operand:V4SF 1 "input_operand" "v,m,v"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1"
! [(set_attr "type" "altivec")])
(define_insn "*set_vrsave_internal"
[(match_parallel 0 "vrsave_operation"
--- 13990,14005 ----
"{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
(define_insn "*movv4sf_internal1"
! [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,m")
! (match_operand:V4SF 1 "input_operand" "v,m,v,r"))]
"TARGET_ALTIVEC"
"@
stvx %1,%y0
lvx %0,%y1
! vor %0,%1,%1
! {st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0"
! [(set_attr "type" "altivec")
! (set_attr "length" "*,*,*,16")])
(define_insn "*set_vrsave_internal"
[(match_parallel 0 "vrsave_operation"
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