RFC: hex constants in const_int (plus small altivec problem)

[Aldy Hernandez]

On Fri, Dec 20, 2002 at 02:29:21PM -0800, Richard Henderson wrote:
> On Fri, Dec 20, 2002 at 01:59:10PM -0800, Aldy Hernandez wrote:
> > Uhhhh, how do you suggest I represent [-0.0, -0.0, -0.0, -0.0] in rtl?
> 
> With const_double, like all other fp constants.  If you mean
> in the md file, don't.  Use predicates.

Thought about this some more.  It's easier to generate the
instructions from the expander.  No weird constants.

This fixes PR 8763 which I've closed.

Committed to mainline and branch.

Aldy

2002-12-23  Aldy Hernandez  <aldyh@redhat.com>

	PR/8763
	* config/rs6000/altivec.md (mulv4sf3): Rewrite to add -0.0 vector.
	(altivec_vspltisw_v4sf): Name pattern.
	(altivec_vslw_v4sf): New pattern.
	
Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.3
diff -c -p -r1.3 altivec.md
*** config/rs6000/altivec.md	19 Dec 2002 23:04:55 -0000	1.3
--- config/rs6000/altivec.md	23 Dec 2002 22:02:10 -0000
***************
*** 490,507 ****
    "vmaddfp %0,%1,%2,%3"
    [(set_attr "type" "vecfloat")])
  
! ;; The unspec here is a vec splat of 0. We do multiply as a fused
! ;; multiply-add with an add of a 0 vector. 
  
  (define_expand "mulv4sf3"
!   [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142))
!    (set (match_operand:V4SF 0 "register_operand" "=v")
!         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
! 	                      (match_operand:V4SF 2 "register_operand" "v"))
! 		   (match_dup 3)))]
    "TARGET_ALTIVEC && TARGET_FUSED_MADD"
    "
! { operands[3] = gen_reg_rtx (V4SFmode); }")
  
  ;; Fused multiply subtract 
  (define_insn "altivec_vnmsubfp"
--- 490,516 ----
    "vmaddfp %0,%1,%2,%3"
    [(set_attr "type" "vecfloat")])
  
! ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
  
  (define_expand "mulv4sf3"
!   [(use (match_operand:V4SF 0 "register_operand" ""))
!    (use (match_operand:V4SF 1 "register_operand" ""))
!    (use (match_operand:V4SF 2 "register_operand" ""))]
    "TARGET_ALTIVEC && TARGET_FUSED_MADD"
    "
! {
!   rtx neg0;
! 
!   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
!   neg0 = gen_reg_rtx (V4SFmode);
!   emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1)));
!   emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
! 
!   /* Use the multiply-add.  */
!   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
! 				  neg0));
!   DONE;
! }")
  
  ;; Fused multiply subtract 
  (define_insn "altivec_vnmsubfp"
***************
*** 1043,1048 ****
--- 1052,1065 ----
    "vslw %0,%1,%2"
    [(set_attr "type" "vecsimple")])
  
+ (define_insn "altivec_vslw_v4sf"
+   [(set (match_operand:V4SF 0 "register_operand" "=v")
+         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
+                       (match_operand:V4SF 2 "register_operand" "v")] 109))]
+   "TARGET_ALTIVEC"
+   "vslw %0,%1,%2"
+   [(set_attr "type" "vecsimple")])
+ 
  (define_insn "altivec_vsl"
    [(set (match_operand:V4SI 0 "register_operand" "=v")
          (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
***************
*** 1315,1321 ****
    "vspltisw %0, %1"
    [(set_attr "type" "vecperm")])
  
! (define_insn ""
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
    "TARGET_ALTIVEC"
--- 1332,1338 ----
    "vspltisw %0, %1"
    [(set_attr "type" "vecperm")])
  
! (define_insn "altivec_vspltisw_v4sf"
    [(set (match_operand:V4SF 0 "register_operand" "=v")
          (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))]
    "TARGET_ALTIVEC"