Fix attributes for SSE/MMX instructions
Jan Hubicka
jh@suse.cz
Sat Apr 27 16:15:00 GMT 2002
Hi
this patch adds a lot of boring stuff to make SSE/MMX scheduling possible.
It adds several sse/mmx subtypes and reorganize the attributes to handle
SSE/MMX as they should.
I've tested it by bootstrapping mainline and on the dfa-branch using new
scheduler description for Athlon.
The insn-attrtab.c code size growth (including scheduler description)
is about 90Kb.
Hope I didn't messed up something important.
Honza
Sun Apr 28 02:15:40 CEST 2002 Jan Hubicka <jh@suse.cz>
* i386.md (type): Add new SSE/MMX subtypes, remove usused fop1.
(mode): Add vector modes
(i387): Kill attribute.
(unit): New attribute.
(length_immediate): Grok new types.
(prefix_data16, prefix_rep, prefix_0f): Fix for SSE/MMX.
(modrm): Use "unit".
(memory): Handle MMX/SSE properly.
(scheduling descriptions): Kill uses of fop1.
(sse, mmx, fp patterns): Set type and mode properly.
*** /p1/cfg10/egcs/gcc/config/i386/i386.md Sat Feb 9 19:53:33 2002
--- i386.md Sun Apr 28 02:12:09 2002
***************
*** 116,139 ****
;; A basic instruction type. Refinements due to arguments to be
;; provided in other attributes.
(define_attr "type"
! "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,mmx,fistp"
(const_string "other"))
;; Main data type used by the insn
! (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI"
(const_string "unknown"))
! ;; Set for i387 operations.
! (define_attr "i387" ""
! (if_then_else (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
! (const_int 1)
! (const_int 0)))
;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate" ""
! (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv,sse,mmx")
(const_int 0)
! (eq_attr "i387" "1")
(const_int 0)
(eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
(symbol_ref "ix86_attr_length_immediate_default(insn,1)")
--- 116,143 ----
;; A basic instruction type. Refinements due to arguments to be
;; provided in other attributes.
(define_attr "type"
! "other,multi,alu1,negnot,alu,icmp,test,imov,imovx,lea,incdec,ishift,imul,idiv,ibr,setcc,push,pop,call,callv,icmov,fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,str,cld,sse,sseadd,ssemul,ssediv,ssemov,ssecmp,ssecvt,sselog,mmx,mmxmov,mmxadd,mmxshft,mmxcmp,mmxcvt,mmxmul,fistp"
(const_string "other"))
;; Main data type used by the insn
! (define_attr "mode" "unknown,none,QI,HI,SI,DI,unknownfp,SF,DF,XF,TI,V4SF,V2DF,V2SF"
(const_string "unknown"))
! ;; The CPU unit operations uses.
! (define_attr "unit" "integer,i387,sse,mmx,unknown"
! (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp")
! (const_string "i387")
! (eq_attr "type" "sse,sseadd,ssemul,ssediv,ssemov,ssecmp,ssecvt,sselog")
! (const_string "sse")
! (eq_attr "type" "mmx,mmxmov,mmxadd,mmxshft,mmxcmp,mmxcvt,mmxmul")
! (const_string "mmx")]
! (const_string "integer")))
;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate" ""
! (cond [(eq_attr "type" "incdec,setcc,icmov,ibr,str,cld,lea,other,multi,idiv")
(const_int 0)
! (eq_attr "unit" "i387,sse,mmx")
(const_int 0)
(eq_attr "type" "alu1,negnot,alu,icmp,imovx,ishift,imul,push,pop")
(symbol_ref "ix86_attr_length_immediate_default(insn,1)")
***************
*** 172,187 ****
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
! (if_then_else (eq_attr "mode" "HI")
(const_int 1)
(const_int 0)))
;; Set when string REP prefix is used.
! (define_attr "prefix_rep" "" (const_int 0))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
! (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,mmx")
(const_int 1)
(const_int 0)))
--- 176,195 ----
;; Set when length prefix is used.
(define_attr "prefix_data16" ""
! (if_then_else (ior (eq_attr "mode" "HI")
! (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF")))
(const_int 1)
(const_int 0)))
;; Set when string REP prefix is used.
! (define_attr "prefix_rep" ""
! (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
! (const_int 1)
! (const_int 0)))
;; Set when 0f opcode prefix is used.
(define_attr "prefix_0f" ""
! (if_then_else (eq_attr "type" "imovx,setcc,icmov,sse,sseadd,ssemul,ssediv,ssemov,ssecmp,ssecvt,sselog,mmx,mmxmov,mmxadd,mmxshft,mmxcmp,mmxcvt,mmxmul")
(const_int 1)
(const_int 0)))
***************
*** 189,195 ****
(define_attr "modrm" ""
(cond [(eq_attr "type" "str,cld")
(const_int 0)
! (eq_attr "i387" "1")
(const_int 0)
(and (eq_attr "type" "incdec")
(ior (match_operand:SI 1 "register_operand" "")
--- 197,203 ----
(define_attr "modrm" ""
(cond [(eq_attr "type" "str,cld")
(const_int 0)
! (eq_attr "unit" "i387")
(const_int 0)
(and (eq_attr "type" "incdec")
(ior (match_operand:SI 1 "register_operand" "")
***************
*** 214,224 ****
(define_attr "length" ""
(cond [(eq_attr "type" "other,multi,fistp")
(const_int 16)
! ]
(plus (plus (attr "modrm")
(plus (attr "prefix_0f")
! (plus (attr "i387")
! (const_int 1))))
(plus (attr "prefix_rep")
(plus (attr "prefix_data16")
(plus (attr "length_immediate")
--- 222,234 ----
(define_attr "length" ""
(cond [(eq_attr "type" "other,multi,fistp")
(const_int 16)
! (eq_attr "unit" "i387")
! (plus (const_int 2)
! (plus (attr "prefix_data16")
! (attr "length_address")))]
(plus (plus (attr "modrm")
(plus (attr "prefix_0f")
! (const_int 1)))
(plus (attr "prefix_rep")
(plus (attr "prefix_data16")
(plus (attr "length_immediate")
***************
*** 270,276 ****
(const_string "store")
(match_operand 1 "memory_operand" "")
(const_string "load")
! (and (eq_attr "type" "!icmp,test,alu1,negnot,fop1,fsgn,imov,imovx,fmov,fcmp,sse,mmx")
(match_operand 2 "memory_operand" ""))
(const_string "load")
(and (eq_attr "type" "icmov")
--- 280,286 ----
(const_string "store")
(match_operand 1 "memory_operand" "")
(const_string "load")
! (and (eq_attr "type" "!icmp,test,alu1,negnot,fsgn,imov,imovx,fmov,fcmp,sse,mmx,ssemov,mmxmov,ssecvt,mmxcvt")
(match_operand 2 "memory_operand" ""))
(const_string "load")
(and (eq_attr "type" "icmov")
***************
*** 518,526 ****
; integer instructions, because of the inpaired fxch instruction.
(define_function_unit "pent_np" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp"))
2 2
! [(eq_attr "type" "!fmov,fop,fop1,fsgn,fmul,fpspc,fcmov,fcmp,fistp")])
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
--- 792,800 ----
; integer instructions, because of the inpaired fxch instruction.
(define_function_unit "pent_np" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fmov,fop,fsgn,fmul,fpspc,fcmov,fcmp,fistp"))
2 2
! [(eq_attr "type" "!fmov,fop,fsgn,fmul,fpspc,fcmov,fcmp,fistp")])
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
***************
*** 531,537 ****
; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fop,fop1,fistp"))
3 1)
; Multiplication takes 3 cycles and is only half pipelined.
--- 805,811 ----
; ??? Trivial fp operations such as fabs or fchs takes only one cycle.
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentium")
! (eq_attr "type" "fop,fistp"))
3 1)
; Multiplication takes 3 cycles and is only half pipelined.
***************
*** 629,635 ****
(define_function_unit "ppro_p0" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fop1,fsgn,fistp"))
3 1)
(define_function_unit "ppro_p0" 1 0
--- 904,910 ----
(define_function_unit "ppro_p0" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fsgn,fistp"))
3 1)
(define_function_unit "ppro_p0" 1 0
***************
*** 682,688 ****
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fop1,fsgn,fmov,fcmp,fcmov,fistp"))
1 1)
(define_function_unit "fpu" 1 0
--- 957,963 ----
(define_function_unit "fpu" 1 0
(and (eq_attr "cpu" "pentiumpro")
! (eq_attr "type" "fop,fsgn,fmov,fcmp,fcmov,fistp"))
1 1)
(define_function_unit "fpu" 1 0
***************
*** 785,791 ****
(define_function_unit "k6_fpu" 1 1
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "fop,fop1,fmov,fcmp,fistp"))
2 2)
(define_function_unit "k6_fpu" 1 1
--- 1060,1066 ----
(define_function_unit "k6_fpu" 1 1
(and (eq_attr "cpu" "k6")
! (eq_attr "type" "fop,fmov,fcmp,fistp"))
2 2)
(define_function_unit "k6_fpu" 1 1
***************
*** 897,903 ****
42 42)
(define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
! (cond [(eq_attr "type" "fop,fop1,fcmp,fistp")
(const_string "add")
(eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
(const_string "mul")
--- 1509,1515 ----
42 42)
(define_attr "athlon_fpunits" "none,store,mul,add,muladd,any"
! (cond [(eq_attr "type" "fop,fcmp,fistp")
(const_string "add")
(eq_attr "type" "fmul,fdiv,fpspc,fsgn,fcmov")
(const_string "mul")
***************
*** 932,938 ****
(define_function_unit "athlon_fp" 3 0
(and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fop,fop1,fmul,fistp"))
4 1)
;; XFmode loads are slow.
--- 1544,1550 ----
(define_function_unit "athlon_fp" 3 0
(and (eq_attr "cpu" "athlon")
! (eq_attr "type" "fop,fmul,fistp"))
4 1)
;; XFmode loads are slow.
***************
*** 1552,1558 ****
"fnstsw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "SI")
! (set_attr "i387" "1")
(set_attr "ppro_uops" "few")])
;; FP compares, step 3
--- 2164,2170 ----
"fnstsw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "SI")
! (set_attr "unit" "i387")
(set_attr "ppro_uops" "few")])
;; FP compares, step 3
***************
*** 1591,1597 ****
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "fcmp,sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
--- 2203,2209 ----
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "fcmp,ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
***************
*** 1602,1608 ****
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
--- 2214,2220 ----
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[0])"
"* return output_fp_compare (insn, operands, 1, 0);"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
***************
*** 1627,1633 ****
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "fcmp,sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
--- 2239,2245 ----
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "fcmp,ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
***************
*** 1638,1644 ****
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "sse")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
--- 2250,2256 ----
"SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, 1, 1);"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "unknownfp")
(set_attr "athlon_decode" "vector")])
***************
*** 1759,1767 ****
}
[(set (attr "type")
(cond [(eq_attr "alternative" "4,5")
! (const_string "mmx")
(eq_attr "alternative" "6,7,8")
! (const_string "sse")
(and (ne (symbol_ref "flag_pic") (const_int 0))
(match_operand:SI 1 "symbolic_operand" ""))
(const_string "lea")
--- 2371,2379 ----
}
[(set (attr "type")
(cond [(eq_attr "alternative" "4,5")
! (const_string "mmxmov")
(eq_attr "alternative" "6,7,8")
! (const_string "ssemov")
(and (ne (symbol_ref "flag_pic") (const_int 0))
(match_operand:SI 1 "symbolic_operand" ""))
(const_string "lea")
***************
*** 2472,2478 ****
movq\t{%1, %0|%0, %1}
movdqa\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,mmx,mmx,sse,sse,sse")
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
(define_split
--- 3084,3090 ----
movq\t{%1, %0|%0, %1}
movdqa\t{%1, %0|%0, %1}
movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,mmx,mmx,ssemov,ssemov,ssemov")
(set_attr "mode" "DI,DI,DI,DI,DI,TI,DI")])
(define_split
***************
*** 2525,2533 ****
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5,6")
! (const_string "mmx")
(eq_attr "alternative" "7,8")
! (const_string "sse")
(eq_attr "alternative" "4")
(const_string "multi")
(and (ne (symbol_ref "flag_pic") (const_int 0))
--- 3137,3145 ----
}
[(set (attr "type")
(cond [(eq_attr "alternative" "5,6")
! (const_string "mmxmov")
(eq_attr "alternative" "7,8")
! (const_string "ssemov")
(eq_attr "alternative" "4")
(const_string "multi")
(and (ne (symbol_ref "flag_pic") (const_int 0))
***************
*** 2770,2776 ****
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,imov,imov,sse,sse,sse,sse,mmx,mmx")
(set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI")])
(define_insn "*swapsf"
--- 3382,3388 ----
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,imov,imov,ssemov,ssemov,ssemov,ssemov,mmxmov,mmxmov")
(set_attr "mode" "SF,SF,SF,SI,SI,TI,SF,SF,SF,SI,SI")])
(define_insn "*swapsf"
***************
*** 2946,2952 ****
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_insn "*movdf_integer"
--- 3558,3564 ----
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_insn "*movdf_integer"
***************
*** 3005,3011 ****
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,sse,sse,sse,sse")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_split
--- 3617,3623 ----
abort();
}
}
! [(set_attr "type" "fmov,fmov,fmov,multi,multi,ssemov,ssemov,ssemov,ssemov")
(set_attr "mode" "DF,DF,DF,SI,SI,TI,DF,DF,DF")])
(define_split
***************
*** 4069,4075 ****
abort ();
}
}
! [(set_attr "type" "fmov,fmov,sse")
(set_attr "mode" "SF,XF,DF")])
(define_insn "*extendsfdf2_1_sse_only"
--- 4681,4687 ----
abort ();
}
}
! [(set_attr "type" "fmov,fmov,ssecvt")
(set_attr "mode" "SF,XF,DF")])
(define_insn "*extendsfdf2_1_sse_only"
***************
*** 4078,4084 ****
"!TARGET_80387 && TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"cvtss2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
(define_expand "extendsfxf2"
--- 4690,4696 ----
"!TARGET_80387 && TARGET_SSE2
&& (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)"
"cvtss2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
(define_expand "extendsfxf2"
***************
*** 4308,4314 ****
abort ();
}
}
! [(set_attr "type" "fmov,multi,multi,multi,sse")
(set_attr "mode" "SF,SF,SF,SF,DF")])
(define_insn "*truncdfsf2_2"
--- 4920,4926 ----
abort ();
}
}
! [(set_attr "type" "fmov,multi,multi,multi,ssecvt")
(set_attr "mode" "SF,SF,SF,SF,DF")])
(define_insn "*truncdfsf2_2"
***************
*** 4331,4337 ****
abort ();
}
}
! [(set_attr "type" "sse,fmov")
(set_attr "mode" "DF,SF")])
(define_insn "truncdfsf2_3"
--- 4943,4949 ----
abort ();
}
}
! [(set_attr "type" "ssecvt,fmov")
(set_attr "mode" "DF,SF")])
(define_insn "truncdfsf2_3"
***************
*** 4354,4360 ****
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
"!TARGET_80387 && TARGET_SSE2"
"cvtsd2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
(define_split
--- 4966,4972 ----
(match_operand:DF 1 "nonimmediate_operand" "mY")))]
"!TARGET_80387 && TARGET_SSE2"
"cvtsd2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")])
(define_split
***************
*** 4771,4784 ****
(fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_64BIT && TARGET_SSE"
"cvttss2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_64BIT && TARGET_SSE2"
"cvttsd2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; Signed conversion to SImode.
--- 5383,5396 ----
(fix:DI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_64BIT && TARGET_SSE"
"cvttss2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
(define_insn "fix_truncdfdi_sse"
[(set (match_operand:DI 0 "register_operand" "=r")
(fix:DI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_64BIT && TARGET_SSE2"
"cvttsd2si{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
;; Signed conversion to SImode.
***************
*** 4879,4892 ****
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "fix_truncdfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
--- 5491,5504 ----
(fix:SI (match_operand:SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
(define_insn "fix_truncdfsi_sse"
[(set (match_operand:SI 0 "register_operand" "=r")
(fix:SI (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"cvttsd2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")])
(define_split
[(set (match_operand:SI 0 "register_operand" "")
***************
*** 5022,5028 ****
"fnstcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "i387" "1")
(set_attr "ppro_uops" "few")])
(define_insn "x86_fldcw_1"
--- 5634,5640 ----
"fnstcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "unit" "i387")
(set_attr "ppro_uops" "few")])
(define_insn "x86_fldcw_1"
***************
*** 5032,5038 ****
"fldcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "i387" "1")
(set_attr "athlon_decode" "vector")
(set_attr "ppro_uops" "few")])
--- 5644,5650 ----
"fldcw\t%0"
[(set_attr "length" "2")
(set_attr "mode" "HI")
! (set_attr "unit" "i387")
(set_attr "athlon_decode" "vector")
(set_attr "ppro_uops" "few")])
***************
*** 5066,5072 ****
fild%z1\t%1
#
cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5678,5684 ----
fild%z1\t%1
#
cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5075,5081 ****
(float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE"
"cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5687,5693 ----
(float:SF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE"
"cvtsi2ss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5104,5110 ****
fild%z1\t%1
#
cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5716,5722 ----
fild%z1\t%1
#
cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5113,5119 ****
(float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_64BIT && TARGET_SSE"
"cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
--- 5725,5731 ----
(float:SF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_64BIT && TARGET_SSE"
"cvtsi2ss{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "SF")
(set_attr "fp_int_src" "true")])
***************
*** 5142,5148 ****
fild%z1\t%1
#
cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5754,5760 ----
fild%z1\t%1
#
cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 5151,5157 ****
(float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5763,5769 ----
(float:DF (match_operand:SI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 5180,5186 ****
fild%z1\t%1
#
cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5792,5798 ----
fild%z1\t%1
#
cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "fmov,multi,ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 5189,5195 ****
(float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
--- 5801,5807 ----
(float:DF (match_operand:DI 1 "nonimmediate_operand" "mr")))]
"TARGET_SSE2"
"cvtsi2sd{q}\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
(set_attr "mode" "DF")
(set_attr "fp_int_src" "true")])
***************
*** 12639,12645 ****
(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
"TARGET_SSE && reload_completed"
"cmp%D1ss\t{%3, %0|%0, %3}"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")])
(define_insn "*sse_setccdf"
--- 13251,13257 ----
(match_operand:SF 3 "nonimmediate_operand" "xm")]))]
"TARGET_SSE && reload_completed"
"cmp%D1ss\t{%3, %0|%0, %3}"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "SF")])
(define_insn "*sse_setccdf"
***************
*** 12649,12655 ****
(match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
"TARGET_SSE2 && reload_completed"
"cmp%D1sd\t{%3, %0|%0, %3}"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
;; Basic conditional jump instructions.
--- 13261,13267 ----
(match_operand:DF 3 "nonimmediate_operand" "Ym")]))]
"TARGET_SSE2 && reload_completed"
"cmp%D1sd\t{%3, %0|%0, %3}"
! [(set_attr "type" "ssecmp")
(set_attr "mode" "DF")])
;; Basic conditional jump instructions.
***************
*** 13879,13885 ****
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (const_string "sse")
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
--- 14491,14499 ----
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd"))
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
***************
*** 13892,13898 ****
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
"TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")])
(define_insn "*fop_df_comm_nosse"
--- 14506,14515 ----
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
"TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set (attr "type")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd")))
(set_attr "mode" "SF")])
(define_insn "*fop_df_comm_nosse"
***************
*** 13919,13925 ****
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (const_string "sse")
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
--- 14536,14544 ----
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(if_then_else (eq_attr "alternative" "1")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd"))
(if_then_else (match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(const_string "fop"))))
***************
*** 13933,13939 ****
"TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")
(set_attr "mode" "DF")])
(define_insn "*fop_xf_comm"
--- 14552,14561 ----
"TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set (attr "type")
! (if_then_else (match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (const_string "sseadd")))
(set_attr "mode" "DF")])
(define_insn "*fop_xf_comm"
***************
*** 13991,13998 ****
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(eq_attr "alternative" "2")
! (const_string "sse")
(match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:SF 3 "div_operator" "")
--- 14613,14626 ----
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(and (eq_attr "alternative" "2")
! (match_operand:SF 3 "mult_operator" ""))
! (const_string "ssemul")
! (and (eq_attr "alternative" "2")
! (match_operand:SF 3 "div_operator" ""))
! (const_string "ssediv")
! (eq_attr "alternative" "2")
! (const_string "sseadd")
(match_operand:SF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:SF 3 "div_operator" "")
***************
*** 14009,14015 ****
"TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")
(set_attr "mode" "SF")])
;; ??? Add SSE splitters for these!
--- 14637,14649 ----
"TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set (attr "type")
! (cond [(match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (match_operand:SF 3 "div_operator" "")
! (const_string "ssediv")
! ]
! (const_string "sseadd")))
(set_attr "mode" "SF")])
;; ??? Add SSE splitters for these!
***************
*** 14061,14067 ****
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
! (match_operand:DF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
--- 14695,14701 ----
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
! (match_operand:DF 3 "div_operator" "")
(const_string "fdiv")
]
(const_string "fop")))
***************
*** 14078,14085 ****
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(eq_attr "alternative" "2")
! (const_string "sse")
(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:DF 3 "div_operator" "")
--- 14712,14725 ----
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
! (cond [(and (eq_attr "alternative" "2")
! (match_operand:SF 3 "mult_operator" ""))
! (const_string "ssemul")
! (and (eq_attr "alternative" "2")
! (match_operand:SF 3 "div_operator" ""))
! (const_string "ssediv")
! (eq_attr "alternative" "2")
! (const_string "sseadd")
(match_operand:DF 3 "mult_operator" "")
(const_string "fmul")
(match_operand:DF 3 "div_operator" "")
***************
*** 14096,14102 ****
"TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "type" "sse")])
;; ??? Add SSE splitters for these!
(define_insn "*fop_df_2"
--- 14736,14749 ----
"TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
! [(set_attr "mode" "DF")
! (set (attr "type")
! (cond [(match_operand:SF 3 "mult_operator" "")
! (const_string "ssemul")
! (match_operand:SF 3 "div_operator" "")
! (const_string "ssediv")
! ]
! (const_string "sseadd")))])
;; ??? Add SSE splitters for these!
(define_insn "*fop_df_2"
***************
*** 17693,17699 ****
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "movv4si_internal"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
--- 18340,18347 ----
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "movv4si_internal"
[(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,m")
***************
*** 17701,17735 ****
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "movv8qi_internal"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
(match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "movv4hi_internal"
[(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
(match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "movv2si_internal"
[(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "movv2sf_internal"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
"TARGET_3DNOW"
"movq\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_expand "movti"
[(set (match_operand:TI 0 "general_operand" "")
--- 18349,18388 ----
"TARGET_SSE"
;; @@@ let's try to use movaps here.
"movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "movv8qi_internal"
[(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m")
(match_operand:V8QI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxmov")
! (set_attr "mode" "DI")])
(define_insn "movv4hi_internal"
[(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m")
(match_operand:V4HI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxmov")
! (set_attr "mode" "DI")])
(define_insn "movv2si_internal"
[(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SI 1 "nonimmediate_operand" "ym,y"))]
"TARGET_MMX"
"movq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "movv2sf_internal"
[(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,m")
(match_operand:V2SF 1 "nonimmediate_operand" "ym,y"))]
"TARGET_3DNOW"
"movq\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_expand "movti"
[(set (match_operand:TI 0 "general_operand" "")
***************
*** 17806,17812 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:TI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv4sf"
[(set (match_operand:V4SF 0 "push_operand" "=<")
--- 18459,18465 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:TI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv4sf"
[(set (match_operand:V4SF 0 "push_operand" "=<")
***************
*** 17817,17823 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SF (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv4si"
[(set (match_operand:V4SI 0 "push_operand" "=<")
--- 18470,18476 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SF (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv4si"
[(set (match_operand:V4SI 0 "push_operand" "=<")
***************
*** 17828,17834 ****
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "sse")])
(define_insn_and_split "*pushv2si"
[(set (match_operand:V2SI 0 "push_operand" "=<")
--- 18481,18487 ----
[(set (reg:SI 7) (plus:SI (reg:SI 7) (const_int -16)))
(set (mem:V4SI (reg:SI 7)) (match_dup 1))]
""
! [(set_attr "type" "multi")])
(define_insn_and_split "*pushv2si"
[(set (match_operand:V2SI 0 "push_operand" "=<")
***************
*** 17882,17888 ****
xorps\t%0, %0
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "*movti_rex64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
--- 18535,18542 ----
xorps\t%0, %0
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov,ssemov,ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "*movti_rex64"
[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o,x,mx,x")
***************
*** 17895,17902 ****
xorps\t%0, %0
movaps\\t{%1, %0|%0, %1}
movaps\\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,sse,sse,sse")
! (set_attr "mode" "TI")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
--- 18549,18556 ----
xorps\t%0, %0
movaps\\t{%1, %0|%0, %1}
movaps\\t{%1, %0|%0, %1}"
! [(set_attr "type" "*,*,ssemov,ssemov,ssemov")
! (set_attr "mode" "V4SF")])
(define_split
[(set (match_operand:TI 0 "nonimmediate_operand" "")
***************
*** 17916,17922 ****
"@
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movups"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
--- 18570,18577 ----
"@
movaps\t{%1, %0|%0, %1}
movaps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov,ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movups"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
***************
*** 17926,17932 ****
"@
movups\t{%1, %0|%0, %1}
movups\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE Strange Moves.
--- 18581,18588 ----
"@
movups\t{%1, %0|%0, %1}
movups\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt,ssecvt")
! (set_attr "mode" "V4SF")])
;; SSE Strange Moves.
***************
*** 17936,17949 ****
(unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
"TARGET_SSE"
"movmskps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "mmx_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmovmskb\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "mmx_maskmovq"
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
--- 18592,18608 ----
(unspec:SI [(match_operand:V4SF 1 "register_operand" "x")] 33))]
"TARGET_SSE"
"movmskps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "mmx_pmovmskb"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] 33))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmovmskb\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
!
(define_insn "mmx_maskmovq"
[(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
***************
*** 17952,17972 ****
"TARGET_SSE || TARGET_3DNOW_A"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movntv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
"TARGET_SSE"
"movntps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movntdi"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
"TARGET_SSE || TARGET_3DNOW_A"
"movntq\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movhlps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18611,18634 ----
"TARGET_SSE || TARGET_3DNOW_A"
;; @@@ check ordering of operands in intel/nonintel syntax
"maskmovq\t{%2, %1|%1, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "sse_movntv4sf"
[(set (match_operand:V4SF 0 "memory_operand" "=m")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "x")] 34))]
"TARGET_SSE"
"movntps\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movntdi"
[(set (match_operand:DI 0 "memory_operand" "=m")
(unspec:DI [(match_operand:DI 1 "register_operand" "y")] 34))]
"TARGET_SSE || TARGET_3DNOW_A"
"movntq\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxmov")
! (set_attr "mode" "DI")])
(define_insn "sse_movhlps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 17980,17986 ****
(const_int 3)))]
"TARGET_SSE"
"movhlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movlhps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18642,18649 ----
(const_int 3)))]
"TARGET_SSE"
"movhlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movlhps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 17994,18000 ****
(const_int 12)))]
"TARGET_SSE"
"movlhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movhps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
--- 18657,18664 ----
(const_int 12)))]
"TARGET_SSE"
"movlhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movhps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
***************
*** 18005,18011 ****
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_movlps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
--- 18669,18676 ----
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_movlps"
[(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,m")
***************
*** 18016,18022 ****
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_loadss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18681,18688 ----
"TARGET_SSE
&& (GET_CODE (operands[1]) == MEM || GET_CODE (operands[2]) == MEM)"
"movlps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_loadss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18026,18032 ****
(const_int 1)))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_movss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18692,18699 ----
(const_int 1)))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "SF")])
(define_insn "sse_movss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18036,18042 ****
(const_int 1)))]
"TARGET_SSE"
"movss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_storess"
[(set (match_operand:SF 0 "memory_operand" "=m")
--- 18703,18710 ----
(const_int 1)))]
"TARGET_SSE"
"movss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "SF")])
(define_insn "sse_storess"
[(set (match_operand:SF 0 "memory_operand" "=m")
***************
*** 18045,18051 ****
(parallel [(const_int 0)])))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_shufps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18713,18720 ----
(parallel [(const_int 0)])))]
"TARGET_SSE"
"movss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssemov")
! (set_attr "mode" "SF")])
(define_insn "sse_shufps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18055,18061 ****
"TARGET_SSE"
;; @@@ check operand order for intel/nonintel syntax
"shufps\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "sse")])
;; SSE arithmetic
--- 18724,18731 ----
"TARGET_SSE"
;; @@@ check operand order for intel/nonintel syntax
"shufps\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
;; SSE arithmetic
***************
*** 18066,18072 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"addps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmaddv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18736,18743 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"addps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V4SF")])
(define_insn "vmaddv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18077,18083 ****
(const_int 1)))]
"TARGET_SSE"
"addss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "subv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18748,18755 ----
(const_int 1)))]
"TARGET_SSE"
"addss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "SF")])
(define_insn "subv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18085,18091 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"subps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsubv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18757,18764 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"subps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "V4SF")])
(define_insn "vmsubv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18096,18102 ****
(const_int 1)))]
"TARGET_SSE"
"subss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18769,18776 ----
(const_int 1)))]
"TARGET_SSE"
"subss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sseadd")
! (set_attr "mode" "SF")])
(define_insn "mulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18104,18110 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"mulps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmmulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18778,18785 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"mulps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemul")
! (set_attr "mode" "V4SF")])
(define_insn "vmmulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18115,18121 ****
(const_int 1)))]
"TARGET_SSE"
"mulss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "divv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18790,18797 ----
(const_int 1)))]
"TARGET_SSE"
"mulss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssemul")
! (set_attr "mode" "SF")])
(define_insn "divv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18123,18129 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"divps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmdivv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18799,18806 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"divps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssediv")
! (set_attr "mode" "V4SF")])
(define_insn "vmdivv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18134,18140 ****
(const_int 1)))]
"TARGET_SSE"
"divss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE square root/reciprocal
--- 18811,18818 ----
(const_int 1)))]
"TARGET_SSE"
"divss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssediv")
! (set_attr "mode" "SF")])
;; SSE square root/reciprocal
***************
*** 18145,18151 ****
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42))]
"TARGET_SSE"
"rcpps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "vmrcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18823,18830 ----
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 42))]
"TARGET_SSE"
"rcpps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmrcpv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18155,18161 ****
(const_int 1)))]
"TARGET_SSE"
"rcpss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18834,18841 ----
(const_int 1)))]
"TARGET_SSE"
"rcpss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
(define_insn "rsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18163,18169 ****
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43))]
"TARGET_SSE"
"rsqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "vmrsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18843,18850 ----
[(match_operand:V4SF 1 "nonimmediate_operand" "xm")] 43))]
"TARGET_SSE"
"rsqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmrsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18173,18186 ****
(const_int 1)))]
"TARGET_SSE"
"rsqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"sqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "vmsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 18854,18869 ----
(const_int 1)))]
"TARGET_SSE"
"rsqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
(define_insn "sqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"sqrtps\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmsqrtv4sf2"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18190,18196 ****
(const_int 1)))]
"TARGET_SSE"
"sqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE logical operations.
--- 18873,18880 ----
(const_int 1)))]
"TARGET_SSE"
"sqrtss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
;; SSE logical operations.
***************
*** 18205,18211 ****
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_andti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18889,18896 ----
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_andti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18213,18219 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_andti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18898,18905 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_andti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18221,18227 ****
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_andti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18907,18914 ----
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_andti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18229,18235 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_andti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18916,18923 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_andti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18237,18243 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_andti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18925,18932 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"andps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_andti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18245,18251 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_nandti3_df"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18934,18941 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "TI")])
(define_insn "*sse_nandti3_df"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18253,18259 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andnpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_nandti3_sf"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18943,18950 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"andnpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_nandti3_sf"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18261,18267 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_nandti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18952,18959 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_nandti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18269,18275 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_nandti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 18961,18968 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"andnps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_nandti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18277,18283 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pnand\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18970,18977 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pnand\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "TI")])
(define_insn "*sse_iorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18285,18291 ****
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 18979,18986 ----
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_iorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18293,18299 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18988,18995 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"orpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_iorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18301,18307 ****
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 18997,19004 ----
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_iorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18309,18315 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_iorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 19006,19013 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_iorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18317,18323 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_iorti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 19015,19022 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"orps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_iorti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18325,18331 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 19024,19031 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "TI")])
(define_insn "*sse_xorti3_df_1"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18333,18339 ****
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
--- 19033,19040 ----
(subreg:TI (match_operand:DF 2 "register_operand" "Y") 0)))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_xorti3_df_2"
[(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0)
***************
*** 18341,18347 ****
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 19042,19049 ----
(match_operand:TI 2 "nonimmediate_operand" "Ym")))]
"TARGET_SSE2"
"xorpd\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V2DF")])
(define_insn "*sse_xorti3_sf_1"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18349,18355 ****
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
--- 19051,19058 ----
(subreg:TI (match_operand:SF 2 "register_operand" "x") 0)))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_xorti3_sf_2"
[(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0)
***************
*** 18357,18363 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_xorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 19060,19067 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "sse_xorti3"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18365,18371 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "*sse_xorti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
--- 19069,19076 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE && !TARGET_SSE2"
"xorps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
(define_insn "*sse_xorti3_sse2"
[(set (match_operand:TI 0 "register_operand" "=x")
***************
*** 18373,18379 ****
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; Use xor, but don't show input operands so they aren't live before
;; this insn.
--- 19078,19085 ----
(match_operand:TI 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE2"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "TI")])
;; Use xor, but don't show input operands so they aren't live before
;; this insn.
***************
*** 18382,18389 ****
(unspec:V4SF [(const_int 0)] 45))]
"TARGET_SSE"
"xorps\t{%0, %0|%0, %0}"
! [(set_attr "type" "sse")
! (set_attr "memory" "none")])
;; SSE mask-generating compares
--- 19088,19095 ----
(unspec:V4SF [(const_int 0)] 45))]
"TARGET_SSE"
"xorps\t{%0, %0|%0, %0}"
! [(set_attr "type" "sselog")
! (set_attr "mode" "V4SF")])
;; SSE mask-generating compares
***************
*** 18394,18400 ****
(match_operand:V4SF 2 "register_operand" "x")]))]
"TARGET_SSE"
"cmp%D3ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "maskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 19100,19107 ----
(match_operand:V4SF 2 "register_operand" "x")]))]
"TARGET_SSE"
"cmp%D3ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "V4SF")])
(define_insn "maskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 18409,18415 ****
else
return "cmpn%D3ps\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "sse")])
(define_insn "vmmaskcmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 19116,19123 ----
else
return "cmpn%D3ps\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "V4SF")])
(define_insn "vmmaskcmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 18421,18427 ****
(const_int 1)))]
"TARGET_SSE"
"cmp%D3ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmmaskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
--- 19129,19136 ----
(const_int 1)))]
"TARGET_SSE"
"cmp%D3ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
(define_insn "vmmaskncmpv4sf3"
[(set (match_operand:V4SI 0 "register_operand" "=x")
***************
*** 18439,18445 ****
else
return "cmpn%D3ss\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "sse")])
(define_insn "sse_comi"
[(set (reg:CCFP 17)
--- 19148,19155 ----
else
return "cmpn%D3ss\t{%2, %0|%0, %2}";
}
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
(define_insn "sse_comi"
[(set (reg:CCFP 17)
***************
*** 18452,18458 ****
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"comiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "sse_ucomi"
[(set (reg:CCFPU 17)
--- 19162,19169 ----
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"comiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
(define_insn "sse_ucomi"
[(set (reg:CCFPU 17)
***************
*** 18465,18471 ****
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"ucomiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; SSE unpack
--- 19176,19183 ----
(parallel [(const_int 0)]))]))]
"TARGET_SSE"
"ucomiss\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecmp")
! (set_attr "mode" "SF")])
;; SSE unpack
***************
*** 18486,18492 ****
(const_int 5)))]
"TARGET_SSE"
"unpckhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sse_unpcklps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 19198,19205 ----
(const_int 5)))]
"TARGET_SSE"
"unpckhps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "sse_unpcklps"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18504,18510 ****
(const_int 5)))]
"TARGET_SSE"
"unpcklps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE min/max
--- 19217,19224 ----
(const_int 5)))]
"TARGET_SSE"
"unpcklps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
;; SSE min/max
***************
*** 18515,18521 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"maxps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsmaxv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 19229,19236 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"maxps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmsmaxv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18526,18532 ****
(const_int 1)))]
"TARGET_SSE"
"maxss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 19241,19248 ----
(const_int 1)))]
"TARGET_SSE"
"maxss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
(define_insn "sminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18534,18540 ****
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"minps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "vmsminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 19250,19257 ----
(match_operand:V4SF 2 "nonimmediate_operand" "xm")))]
"TARGET_SSE"
"minps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "V4SF")])
(define_insn "vmsminv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18545,18551 ****
(const_int 1)))]
"TARGET_SSE"
"minss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; SSE <-> integer/MMX conversions
--- 19262,19269 ----
(const_int 1)))]
"TARGET_SSE"
"minss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")
! (set_attr "mode" "SF")])
;; SSE <-> integer/MMX conversions
***************
*** 18559,18565 ****
(const_int 12)))]
"TARGET_SSE"
"cvtpi2ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "cvtps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19277,19284 ----
(const_int 12)))]
"TARGET_SSE"
"cvtpi2ps\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "cvtps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18568,18574 ****
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvtps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19287,19294 ----
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvtps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "V4SF")])
(define_insn "cvttps2pi"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18577,18583 ****
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvttps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvtsi2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
--- 19297,19304 ----
(parallel [(const_int 0) (const_int 1)])))]
"TARGET_SSE"
"cvttps2pi\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
(define_insn "cvtsi2ss"
[(set (match_operand:V4SF 0 "register_operand" "=x")
***************
*** 18588,18594 ****
(const_int 14)))]
"TARGET_SSE"
"cvtsi2ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "cvtss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 19309,19316 ----
(const_int 14)))]
"TARGET_SSE"
"cvtsi2ss\t{%2, %0|%0, %2}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
(define_insn "cvtss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 18597,18603 ****
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvtss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
(define_insn "cvttss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 19319,19326 ----
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvtss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
(define_insn "cvttss2si"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 18606,18612 ****
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "sse")])
;; MMX insns
--- 19329,19336 ----
(parallel [(const_int 0)])))]
"TARGET_SSE"
"cvttss2si\t{%1, %0|%0, %1}"
! [(set_attr "type" "ssecvt")
! (set_attr "mode" "SF")])
;; MMX insns
***************
*** 18619,18625 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "addv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19343,19350 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "addv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18627,18633 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "addv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19352,19359 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "addv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18635,18641 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ssaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19361,19368 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ssaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18643,18649 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ssaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19370,19377 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ssaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18651,18657 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "usaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19379,19386 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "usaddv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18659,18665 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "usaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19388,19395 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "usaddv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18667,18673 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19397,19404 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"paddusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "subv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18675,18681 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19406,19413 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "subv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18683,18689 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19415,19422 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "subv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18691,18697 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "sssubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19424,19431 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "sssubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18699,18705 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "sssubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19433,19440 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "sssubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18707,18713 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ussubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19442,19449 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ussubv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18715,18721 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ussubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19451,19458 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "ussubv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18723,18729 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mulv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19460,19467 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"psubusw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "mulv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18731,18737 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pmullw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "smulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19469,19476 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pmullw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
(define_insn "smulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18744,18750 ****
(const_int 16))))]
"TARGET_MMX"
"pmulhw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "umulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19483,19490 ----
(const_int 16))))]
"TARGET_MMX"
"pmulhw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
(define_insn "umulv4hi3_highpart"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18757,18763 ****
(const_int 16))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmulhuw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_pmaddwd"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19497,19504 ----
(const_int 16))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmulhuw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
(define_insn "mmx_pmaddwd"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18778,18784 ****
(const_int 3)]))))))]
"TARGET_MMX"
"pmaddwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX logical operations
--- 19519,19526 ----
(const_int 3)]))))))]
"TARGET_MMX"
"pmaddwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "DI")])
;; MMX logical operations
***************
*** 18792,18798 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_xordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
--- 19534,19541 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"por\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "mmx_xordi3"
[(set (match_operand:DI 0 "register_operand" "=y")
***************
*** 18801,18807 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
(set_attr "memory" "none")])
;; Same as pxor, but don't show input operands so that we don't think
--- 19544,19551 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pxor\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")
(set_attr "memory" "none")])
;; Same as pxor, but don't show input operands so that we don't think
***************
*** 18811,18817 ****
(unspec:DI [(const_int 0)] 45))]
"TARGET_MMX"
"pxor\t{%0, %0|%0, %0}"
! [(set_attr "type" "mmx")
(set_attr "memory" "none")])
(define_insn "mmx_anddi3"
--- 19555,19562 ----
(unspec:DI [(const_int 0)] 45))]
"TARGET_MMX"
"pxor\t{%0, %0|%0, %0}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")
(set_attr "memory" "none")])
(define_insn "mmx_anddi3"
***************
*** 18821,18827 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_nanddi3"
[(set (match_operand:DI 0 "register_operand" "=y")
--- 19566,19573 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pand\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "mmx_nanddi3"
[(set (match_operand:DI 0 "register_operand" "=y")
***************
*** 18830,18836 ****
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pandn\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX unsigned averages/sum of absolute differences
--- 19576,19583 ----
(match_operand:DI 2 "nonimmediate_operand" "ym"))] 45))]
"TARGET_MMX"
"pandn\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
;; MMX unsigned averages/sum of absolute differences
***************
*** 18852,18858 ****
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgb\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mmx_uavgv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19599,19606 ----
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_uavgv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18867,18873 ****
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "mmx_psadbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19615,19622 ----
(const_int 1)))]
"TARGET_SSE || TARGET_3DNOW_A"
"pavgw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_psadbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18875,18881 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
"TARGET_SSE || TARGET_3DNOW_A"
"psadbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX insert/extract/shuffle
--- 19624,19631 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym"))))]
"TARGET_SSE || TARGET_3DNOW_A"
"psadbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; MMX insert/extract/shuffle
***************
*** 18888,18894 ****
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "sse")])
(define_insn "mmx_pextrw"
[(set (match_operand:SI 0 "register_operand" "=r")
--- 19638,19645 ----
(match_operand:SI 3 "immediate_operand" "i")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pinsrw\t{%3, %2, %0|%0, %2, %3}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_pextrw"
[(set (match_operand:SI 0 "register_operand" "=r")
***************
*** 18897,18903 ****
[(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
(define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19648,19655 ----
[(match_operand:SI 2 "immediate_operand" "i")]))))]
"TARGET_SSE || TARGET_3DNOW_A"
"pextrw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_pshufw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18905,18911 ****
(match_operand:SI 2 "immediate_operand" "i")] 41))]
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "sse")])
;; MMX mask-generating comparisons
--- 19657,19664 ----
(match_operand:SI 2 "immediate_operand" "i")] 41))]
"TARGET_SSE || TARGET_3DNOW_A"
"pshufw\t{%2, %1, %0|%0, %1, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
;; MMX mask-generating comparisons
***************
*** 18916,18922 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "eqv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19669,19676 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "eqv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18924,18930 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "eqv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19678,19685 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "eqv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18932,18938 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19687,19694 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpeqd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "gtv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18940,18946 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19696,19703 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "gtv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18948,18954 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19705,19712 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
(define_insn "gtv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 18956,18962 ****
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX max/min insns
--- 19714,19721 ----
(match_operand:V2SI 2 "nonimmediate_operand" "ym")))]
"TARGET_MMX"
"pcmpgtd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "DI")])
;; MMX max/min insns
***************
*** 18967,18973 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "smaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19726,19733 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxub\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "smaxv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18975,18981 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "uminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19735,19742 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pmaxsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "uminv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 18983,18989 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminub\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
(define_insn "sminv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19744,19751 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminub\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
(define_insn "sminv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 18991,18997 ****
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "sse")])
;; MMX shifts
--- 19753,19760 ----
(match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
"TARGET_SSE || TARGET_3DNOW_A"
"pminsw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "DI")])
;; MMX shifts
***************
*** 19002,19008 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psraw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ashrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19765,19772 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psraw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "ashrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19010,19016 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrad\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "lshrv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19774,19781 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrad\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "lshrv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19018,19024 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrlw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "lshrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19783,19790 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrlw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "lshrv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19026,19032 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; See logical MMX insns.
(define_insn "mmx_lshrdi3"
--- 19792,19799 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psrld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; See logical MMX insns.
(define_insn "mmx_lshrdi3"
***************
*** 19036,19042 ****
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psrlq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ashlv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19803,19810 ----
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psrlq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "ashlv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19044,19050 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psllw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "ashlv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19812,19819 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"psllw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "ashlv2si3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19052,19058 ****
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"pslld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; See logical MMX insns.
(define_insn "mmx_ashldi3"
--- 19821,19828 ----
(match_operand:DI 2 "nonmemory_operand" "yi")))]
"TARGET_MMX"
"pslld\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; See logical MMX insns.
(define_insn "mmx_ashldi3"
***************
*** 19062,19068 ****
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psllq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; MMX pack/unpack insns.
--- 19832,19839 ----
(match_operand:DI 2 "nonmemory_operand" "yi"))] 45))]
"TARGET_MMX"
"psllq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
;; MMX pack/unpack insns.
***************
*** 19074,19080 ****
(ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packsswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_packssdw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19845,19852 ----
(ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packsswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_packssdw"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19083,19089 ****
(ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packssdw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_packuswb"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19855,19862 ----
(ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packssdw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_packuswb"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19092,19098 ****
(us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packuswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckhbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19865,19872 ----
(us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
"TARGET_MMX"
"packuswb\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckhbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19118,19124 ****
(const_int 85)))]
"TARGET_MMX"
"punpckhbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckhwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19892,19899 ----
(const_int 85)))]
"TARGET_MMX"
"punpckhbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckhwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19136,19142 ****
(const_int 5)))]
"TARGET_MMX"
"punpckhwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckhdq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19911,19918 ----
(const_int 5)))]
"TARGET_MMX"
"punpckhwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckhdq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19150,19156 ****
(const_int 1)))]
"TARGET_MMX"
"punpckhdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpcklbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
--- 19926,19933 ----
(const_int 1)))]
"TARGET_MMX"
"punpckhdq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpcklbw"
[(set (match_operand:V8QI 0 "register_operand" "=y")
***************
*** 19176,19182 ****
(const_int 85)))]
"TARGET_MMX"
"punpcklbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpcklwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 19953,19960 ----
(const_int 85)))]
"TARGET_MMX"
"punpcklbw\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpcklwd"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19194,19200 ****
(const_int 5)))]
"TARGET_MMX"
"punpcklwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mmx_punpckldq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 19972,19979 ----
(const_int 5)))]
"TARGET_MMX"
"punpcklwd\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
(define_insn "mmx_punpckldq"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19208,19214 ****
(const_int 1)))]
"TARGET_MMX"
"punpckldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; Miscellaneous stuff
--- 19987,19994 ----
(const_int 1)))]
"TARGET_MMX"
"punpckldq\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "DI")])
;; Miscellaneous stuff
***************
*** 19337,19343 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfadd\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20117,20124 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfadd\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "subv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19345,19351 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfsub\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "subrv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20126,20133 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfsub\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "subrv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19353,19359 ****
(match_operand:V2SF 1 "register_operand" "0")))]
"TARGET_3DNOW"
"pfsubr\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gtv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 20135,20142 ----
(match_operand:V2SF 1 "register_operand" "0")))]
"TARGET_3DNOW"
"pfsubr\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "gtv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19361,19367 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpgt\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "gev2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 20144,20151 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpgt\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "V2SF")])
(define_insn "gev2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19369,19375 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpge\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "eqv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 20153,20160 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpge\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "V2SF")])
(define_insn "eqv2sf3"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19377,19383 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpeq\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfmaxv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20162,20169 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfcmpeq\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxcmp")
! (set_attr "mode" "V2SF")])
(define_insn "pfmaxv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19385,19391 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmax\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfminv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20171,20178 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmax\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pfminv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19393,19399 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmin\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20180,20187 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmin\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19401,19407 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmul\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "femms"
[(unspec_volatile [(const_int 0)] 46)
--- 20189,20196 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pfmul\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "V2SF")])
(define_insn "femms"
[(unspec_volatile [(const_int 0)] 46)
***************
*** 19430,19436 ****
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pf2id\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pf2iw"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 20219,20226 ----
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pf2id\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
(define_insn "pf2iw"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19439,19445 ****
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
"TARGET_3DNOW_A"
"pf2iw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pfacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20229,20236 ----
(fix:V2SI (match_operand:V2SF 1 "nonimmediate_operand" "ym")))))]
"TARGET_3DNOW_A"
"pf2iw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
(define_insn "pfacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19456,19462 ****
(parallel [(const_int 1)])))))]
"TARGET_3DNOW"
"pfacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20247,20254 ----
(parallel [(const_int 1)])))))]
"TARGET_3DNOW"
"pfacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pfnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19473,19479 ****
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfpnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20265,20272 ----
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pfpnacc"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19490,19496 ****
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfpnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pi2fw"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20283,20290 ----
(parallel [(const_int 1)])))))]
"TARGET_3DNOW_A"
"pfpnacc\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxadd")
! (set_attr "mode" "V2SF")])
(define_insn "pi2fw"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19506,19519 ****
(parallel [(const_int 1)])))))))]
"TARGET_3DNOW_A"
"pi2fw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "floatv2si2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pi2fd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
;; This insn is identical to pavgb in operation, but the opcode is
;; different. To avoid accidentally matching pavgb, use an unspec.
--- 20300,20315 ----
(parallel [(const_int 1)])))))))]
"TARGET_3DNOW_A"
"pi2fw\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
(define_insn "floatv2si2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(float:V2SF (match_operand:V2SI 1 "nonimmediate_operand" "ym")))]
"TARGET_3DNOW"
"pi2fd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "V2SF")])
;; This insn is identical to pavgb in operation, but the opcode is
;; different. To avoid accidentally matching pavgb, use an unspec.
***************
*** 19525,19531 ****
(match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))]
"TARGET_3DNOW"
"pavgusb\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
;; 3DNow reciprical and sqrt
--- 20321,20328 ----
(match_operand:V8QI 2 "nonimmediate_operand" "ym")] 49))]
"TARGET_3DNOW"
"pavgusb\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxshft")
! (set_attr "mode" "TI")])
;; 3DNow reciprical and sqrt
***************
*** 19534,19540 ****
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))]
"TARGET_3DNOW"
"pfrcp\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pfrcpit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20331,20338 ----
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 50))]
"TARGET_3DNOW"
"pfrcp\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrcpit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19542,19548 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))]
"TARGET_3DNOW"
"pfrcpit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfrcpit2v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20340,20347 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 51))]
"TARGET_3DNOW"
"pfrcpit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrcpit2v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19550,19563 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))]
"TARGET_3DNOW"
"pfrcpit2\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pfrsqrtv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))]
"TARGET_3DNOW"
! "pfrsqrt\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pfrsqit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20349,20364 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 52))]
"TARGET_3DNOW"
"pfrcpit2\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrsqrtv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(unspec:V2SF [(match_operand:V2SF 1 "nonimmediate_operand" "ym")] 53))]
"TARGET_3DNOW"
! "pfrsqrt\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pfrsqit1v2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19565,19571 ****
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))]
"TARGET_3DNOW"
"pfrsqit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pmulhrwv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
--- 20366,20373 ----
(match_operand:V2SF 2 "nonimmediate_operand" "ym")] 54))]
"TARGET_3DNOW"
"pfrsqit1\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")
! (set_attr "mode" "TI")])
(define_insn "pmulhrwv4hi3"
[(set (match_operand:V4HI 0 "register_operand" "=y")
***************
*** 19585,19591 ****
(const_int 16))))]
"TARGET_3DNOW"
"pmulhrw\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmx")])
(define_insn "pswapdv2si2"
[(set (match_operand:V2SI 0 "register_operand" "=y")
--- 20387,20394 ----
(const_int 16))))]
"TARGET_3DNOW"
"pmulhrw\\t{%2, %0|%0, %2}"
! [(set_attr "type" "mmxmul")
! (set_attr "mode" "TI")])
(define_insn "pswapdv2si2"
[(set (match_operand:V2SI 0 "register_operand" "=y")
***************
*** 19593,19599 ****
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_insn "pswapdv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
--- 20396,20403 ----
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "TI")])
(define_insn "pswapdv2sf2"
[(set (match_operand:V2SF 0 "register_operand" "=y")
***************
*** 19601,19607 ****
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmx")])
(define_expand "prefetch"
[(prefetch (match_operand:SI 0 "address_operand" "")
--- 20405,20412 ----
(parallel [(const_int 1) (const_int 0)])))]
"TARGET_3DNOW_A"
"pswapd\\t{%1, %0|%0, %1}"
! [(set_attr "type" "mmxcvt")
! (set_attr "mode" "TI")])
(define_expand "prefetch"
[(prefetch (match_operand:SI 0 "address_operand" "")
***************
*** 19643,19649 ****
return patterns[locality];
}
! [(set_attr "type" "sse")])
(define_insn "*prefetch_3dnow"
[(prefetch (match_operand:SI 0 "address_operand" "p")
--- 20448,20455 ----
return patterns[locality];
}
! [(set_attr "type" "sse")
! (set_attr "memory" "none")])
(define_insn "*prefetch_3dnow"
[(prefetch (match_operand:SI 0 "address_operand" "p")
***************
*** 19656,19659 ****
else
return "prefetchw\t%a0";
}
! [(set_attr "type" "mmx")])
--- 20462,20466 ----
else
return "prefetchw\t%a0";
}
! [(set_attr "type" "mmx")
! (set_attr "memory" "none")])
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