[PATCH] add IA-64 operand constraints to doc/md.texi

[Steve Christiansen]

The following patch to doc/md.texi adds a list of machine-dependent
operand constraints for IA-64.  One point deserves an explanation:

Normally the common constraints such as m and r are not included in
the machine lists, but I put m under IA-64 so that I could include
a warning to always use the %P print code with the m constraint.
It's easy to forget, and was the motivation for this patch in the
first place (http://gcc.gnu.org/ml/gcc/2002-04/msg00649.html).

If the patch is ok, could someone apply it?  I don't have write access.

Thanks

Steve


2002-04-24  Steve Christiansen  <smc@us.ibm.com>

	* doc/md.texi (Machine Constraints): Add IA-64 constraints.

Index: gcc/doc/md.texi
===================================================================
RCS file: /cvsroot/gcc/gcc/gcc/doc/md.texi,v
retrieving revision 1.37
diff -c -r1.37 md.texi
*** gcc/doc/md.texi	8 Apr 2002 17:20:48 -0000	1.37
--- gcc/doc/md.texi	24 Apr 2002 19:41:47 -0000
***************
*** 1679,1684 ****
--- 1679,1747 ----
  Floating point 1
  @end table
  
+ @item Intel IA-64---@file{ia64.h}
+ @table @code
+ @item a
+ General register @code{r0} to @code{r3} for @code{addl} instruction
+ 
+ @item b
+ Branch register
+ 
+ @item c
+ Predicate register (@samp{c} as in ``conditional'')
+ 
+ @item d
+ Application register residing in M-unit
+ 
+ @item e
+ Application register residing in I-unit
+ 
+ @item f
+ Floating-point register
+ 
+ @item m
+ Memory operand.
+ Remember that @samp{m} allows postincrement and postdecrement which
+ require printing with @samp{%Pn} on IA-64.
+ Use @samp{S} to disallow postincrement and postdecrement.
+ 
+ @item G
+ Floating-point constant 0.0 or 1.0
+ 
+ @item I
+ 14-bit signed integer constant
+ 
+ @item J
+ 22-bit signed integer constant
+ 
+ @item K
+ 8-bit signed integer constant for logical instructions
+ 
+ @item L
+ 8-bit adjusted signed integer constant for compare pseudo-ops
+ 
+ @item M
+ 6-bit unsigned integer constant for shift counts
+ 
+ @item N
+ 9-bit signed integer constant for load and store postincrements
+ 
+ @item O
+ The constant zero
+ 
+ @item P
+ 0 or -1 for @code{dep} instruction
+ 
+ @item Q
+ Non-volatile memory for floating-point loads and stores
+ 
+ @item R
+ Integer constant in the range 1 to 4 for @code{shladd} instruction
+ 
+ @item S
+ Memory operand except postincrement and postdecrement
+ @end table
+ 
  @item MIPS---@file{mips.h}
  @table @code
  @item d