zext_register_operand related fixes, take 2
Jan Hubicka
jh@suse.cz
Thu May 31 10:16:00 GMT 2001
Hi,
this patch unifies all my previous changes to this area. It has received quite
a lot of testing and new bugs don't seems to be comming anymore.
Thu May 31 19:13:38 CEST 2001 Jan Hubicka <jh@suse.cz>
* i386.md (all uses of ext_register_operand): Make sure they are
VOIDmode; replace all uses outside zero_extend.
(and?i splitters): Use ext_register_operands.
(test?i peep2): Remove ignored constraints.
* i386.c (ext_register_operand): Check that operand is
eighter pseudo or hard or 'Q' register.
*** i386.md Sat May 26 03:02:18 2001
--- /home/hubicka/x86-64/gcc/gcc/config/i386/i386.md Sat May 26 02:49:54 2001
***************
*** 1220,1226 ****
(define_insn "*cmpqi_ext_1_rex64"
[(set (reg 17)
(compare
! (match_operand:QI 0 "ext_register_operand" "Q")
(subreg:QI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "Q")
--- 1222,1228 ----
(define_insn "*cmpqi_ext_1_rex64"
[(set (reg 17)
(compare
! (match_operand:QI 0 "register_operand" "Q")
(subreg:QI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "Q")
***************
*** 2142,2148 ****
(define_insn "*movsi_extv_1"
[(set (match_operand:SI 0 "register_operand" "=R")
! (sign_extract:SI (match_operand:SI 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))]
""
--- 2144,2150 ----
(define_insn "*movsi_extv_1"
[(set (match_operand:SI 0 "register_operand" "=R")
! (sign_extract:SI (match_operand 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))]
""
***************
*** 2152,2158 ****
(define_insn "*movhi_extv_1"
[(set (match_operand:HI 0 "register_operand" "=R")
! (sign_extract:HI (match_operand:SI 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))]
""
--- 2154,2160 ----
(define_insn "*movhi_extv_1"
[(set (match_operand:HI 0 "register_operand" "=R")
! (sign_extract:HI (match_operand 1 "ext_register_operand" "Q")
(const_int 8)
(const_int 8)))]
""
***************
*** 2162,2168 ****
(define_insn "*movqi_extv_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
! (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
(const_int 8)
(const_int 8)))]
"!TARGET_64BIT"
--- 2164,2170 ----
(define_insn "*movqi_extv_1"
[(set (match_operand:QI 0 "nonimmediate_operand" "=Qm,?r")
! (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
(const_int 8)
(const_int 8)))]
"!TARGET_64BIT"
***************
*** 2190,2196 ****
(define_insn "*movqi_extv_1_rex64"
[(set (match_operand:QI 0 "register_operand" "=Q,?R")
! (sign_extract:QI (match_operand:SI 1 "ext_register_operand" "Q,Q")
(const_int 8)
(const_int 8)))]
"TARGET_64BIT"
--- 2192,2198 ----
(define_insn "*movqi_extv_1_rex64"
[(set (match_operand:QI 0 "register_operand" "=Q,?R")
! (sign_extract:QI (match_operand 1 "ext_register_operand" "Q,Q")
(const_int 8)
(const_int 8)))]
"TARGET_64BIT"
***************
*** 2327,2333 ****
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
! (match_operand:SI 1 "ext_register_operand" "Q"))]
"TARGET_64BIT"
"mov{b}\\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
--- 2329,2335 ----
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
! (match_operand:SI 1 "register_operand" "Q"))]
"TARGET_64BIT"
"mov{b}\\t{%b1, %h0|%h0, %b1}"
[(set_attr "type" "imov")
***************
*** 2337,2343 ****
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
! (and:SI (lshiftrt:SI (match_operand:SI 1 "ext_register_operand" "Q")
(const_int 8))
(const_int 255)))]
""
--- 2339,2345 ----
[(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
(const_int 8)
(const_int 8))
! (and:SI (lshiftrt:SI (match_operand:SI 1 "register_operand" "Q")
(const_int 8))
(const_int 255)))]
""
***************
*** 6777,6783 ****
(define_insn "addqi_ext_1"
! [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
(const_int 8)
(const_int 8))
(plus:SI
--- 6810,6816 ----
(define_insn "addqi_ext_1"
! [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
(const_int 8)
(const_int 8))
(plus:SI
***************
*** 6785,6791 ****
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
! (match_operand:QI 2 "general_operand" "qmn")))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
"*
--- 6818,6824 ----
(match_operand 1 "ext_register_operand" "0")
(const_int 8)
(const_int 8))
! (match_operand:QI 2 "general_operand" "Qmn")))
(clobber (reg:CC 17))]
"!TARGET_64BIT"
"*
***************
*** 8055,8061 ****
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand:QI 1 "ext_register_operand" "Q")))
(const_int 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"test{b}\\t{%1, %h0|%h0, %1}"
--- 8121,8127 ----
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand:QI 1 "register_operand" "Q")))
(const_int 0)))]
"TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
"test{b}\\t{%1, %h0|%h0, %1}"
***************
*** 8271,8306 ****
(set_attr "mode" "SI")])
(define_split
! [(set (match_operand 0 "q_regs_operand" "")
(and (match_dup 0)
(const_int -65536)))
(clobber (reg:CC 17))]
! "optimize_size
! && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
! || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (HImode, operands[0]);")
(define_split
! [(set (match_operand 0 "q_regs_operand" "")
(and (match_dup 0)
(const_int -256)))
(clobber (reg:CC 17))]
! "(optimize_size || !TARGET_PARTIAL_REG_STALL)
! && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
! || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (QImode, operands[0]);")
(define_split
! [(set (match_operand 0 "q_regs_operand" "")
(and (match_dup 0)
(const_int -65281)))
(clobber (reg:CC 17))]
! "(optimize_size || !TARGET_PARTIAL_REG_STALL)
! && (GET_MODE (operands[0]) == SImode || GET_MODE (operands[0]) == HImode
! || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
! && (! reload_completed || ANY_QI_REG_P (operands[0]))"
[(parallel [(set (zero_extract:SI (match_dup 0)
(const_int 8)
(const_int 8))
--- 8349,8377 ----
(set_attr "mode" "SI")])
(define_split
! [(set (match_operand 0 "ext_register_operand" "")
(and (match_dup 0)
(const_int -65536)))
(clobber (reg:CC 17))]
! "optimize_size"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (HImode, operands[0]);")
(define_split
! [(set (match_operand 0 "ext_register_operand" "")
(and (match_dup 0)
(const_int -256)))
(clobber (reg:CC 17))]
! "(optimize_size || !TARGET_PARTIAL_REG_STALL)"
[(set (strict_low_part (match_dup 1)) (const_int 0))]
"operands[1] = gen_lowpart (QImode, operands[0]);")
(define_split
! [(set (match_operand 0 "ext_register_operand" "")
(and (match_dup 0)
(const_int -65281)))
(clobber (reg:CC 17))]
! "(optimize_size || !TARGET_PARTIAL_REG_STALL)"
[(parallel [(set (zero_extract:SI (match_dup 0)
(const_int 8)
(const_int 8))
***************
*** 8501,8507 ****
(and:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
! (const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n"))
(const_int 0)))
--- 8572,8578 ----
(and:SI
(zero_extract:SI
(match_operand 1 "ext_register_operand" "0")
! (const_int 8)
(const_int 8))
(match_operand 2 "const_int_operand" "n"))
(const_int 0)))
***************
*** 8549,8555 ****
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand:QI 2 "ext_register_operand" "Q"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
"and{b}\\t{%2, %h0|%h0, %2}"
--- 8620,8626 ----
(const_int 8)
(const_int 8))
(zero_extend:SI
! (match_operand 2 "register_operand" "Q"))))
(clobber (reg:CC 17))]
"TARGET_64BIT"
"and{b}\\t{%2, %h0|%h0, %2}"
***************
*** 16835,16844 ****
(compare
(and:SI
(zero_extract:SI
! (match_operand 0 "ext_register_operand" "q")
(const_int 8)
(const_int 8))
! (match_operand 1 "const_int_operand" "n"))
(const_int 0)))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
--- 16883,16892 ----
(compare
(and:SI
(zero_extract:SI
! (match_operand 0 "ext_register_operand" "")
(const_int 8)
(const_int 8))
! (match_operand 1 "const_int_operand" ""))
(const_int 0)))]
"! TARGET_PARTIAL_REG_STALL
&& ix86_match_ccmode (insn, CCNOmode)
*** i386.c Wed May 23 13:52:39 2001
--- /home/hubicka/x86-64/gcc/gcc/config/i386/i386.c Sat May 26 02:52:04 2001
*************** ext_register_operand (op, mode)
*** 1694,1703 ****
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
if ((!TARGET_64BIT || GET_MODE (op) != DImode)
&& GET_MODE (op) != SImode && GET_MODE (op) != HImode)
return 0;
! return register_operand (op, VOIDmode);
}
/* Return 1 if this is a valid binary floating-point operation.
--- 2681,2697 ----
register rtx op;
enum machine_mode mode ATTRIBUTE_UNUSED;
{
+ int regno;
if ((!TARGET_64BIT || GET_MODE (op) != DImode)
&& GET_MODE (op) != SImode && GET_MODE (op) != HImode)
return 0;
!
! if (!register_operand (op, VOIDmode))
! return 0;
!
! /* Be curefull to accept only registers having upper parts. */
! regno = REG_P (op) ? REGNO (op) : REGNO (SUBREG_REG (op));
! return (regno > LAST_VIRTUAL_REGISTER || regno < 4);
}
/* Return 1 if this is a valid binary floating-point operation.
More information about the Gcc-patches
mailing list