[PATCH]: Fix shift, call, zero_extend and tst patterns in m68hc11.md

[Stephane Carrez]

Hi!

I fixed some problems in m68hc11.md:

 - Some shift insn clobber the operand 2, this is identified by
   a clobber, but the constraint of operand 2 missed a '+' that
   tells reload the register is also modified.

 - The call and call_value patterns were accepting registers
   but they should only accept a memory operand.

I've committed this patch in 3.0 branch.

	Stephane

2001-03-04  Stephane Carrez  <Stephane.Carrez@worldnet.fr>

	* config/m68hc11/m68hc11.md (tsthi_1): Use cpd for 68HC12.
	(zero_extendsi split): Simplify and use (zero_extendhi).
	(*addhi3): Remove 'w' constraint since stack pointer is handled 
	by (addhi3_sp).
	(*ashlhi3_2): Operand 2 is clobbered use '+' for its constraint.
	(*ashlhi3, *ashrhi3, *lshrhi3): Likewise.
	(*ashrhi3_const): Fix shift by 7.
	(*lshrsi3_const16): Fix template.
	(call, call_value): Fix constraint and predicate.
Index: config/m68hc11/m68hc11.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/m68hc11/m68hc11.md,v
retrieving revision 1.3.4.1
diff -u -r1.3.4.1 m68hc11.md
--- m68hc11.md	2001/03/04 09:42:03	1.3.4.1
+++ m68hc11.md	2001/03/04 10:24:06
@@ -115,6 +115,10 @@
 ;;   Such split pattern must also be valid when z_replacement_completed == 2
 ;;   because flow/cse is not aware that D is composed of {a, b}.
 ;;
+;; o Split patterns that generate a (mem:QI (symbol_reg _.dx)) to access
+;;   the high part of a soft register must be expanded after z_replacement
+;;   pass.
+;;
 ;;---------------------------------------------------------------------------
 ;; Constants
 
@@ -170,7 +174,7 @@
   ""
   "*
 {
-   if (D_REG_P (operands[0]))
+   if (D_REG_P (operands[0]) && !TARGET_M6812)
      return \"std\\t%t0\";
    else
      return \"cp%0\\t#0\";
@@ -1062,15 +1066,11 @@
   [(set (match_operand:SI 0 "non_push_operand" "=mu")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dxy")))]
   "reload_completed && !X_REG_P (operands[0])"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 4) (const_int 0))
-   (set (match_dup 5) (const_int 0))]
+  [(set (match_dup 2) (zero_extend:HI (match_dup 1)))
+   (set (match_dup 3) (const_int 0))]
   "
    operands[2] = m68hc11_gen_lowpart (HImode, operands[0]);
-   operands[3] = gen_rtx (REG, HImode, REGNO (operands[1]));
-   operands[4] = m68hc11_gen_lowpart (HImode, operands[0]);
-   operands[4] = m68hc11_gen_highpart (QImode, operands[4]);
-   operands[5] = m68hc11_gen_highpart (HImode, operands[0]);")
+   operands[3] = m68hc11_gen_highpart (HImode, operands[0]);")
 
 (define_split 
   [(set (match_operand:SI 0 "hard_reg_operand" "=D")
@@ -1936,9 +1936,9 @@
   "")
 
 (define_insn "*addhi3"
-  [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d,!w")
-	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0,0")
-		 (match_operand:HI 2 "general_operand" "N,i,I,umi*A*d,!*d*w,i")))]
+  [(set (match_operand:HI 0 "hard_reg_operand" "=A,d,!A,d*A,!d")
+	(plus:HI (match_operand:HI 1 "general_operand" "%0,0,0,0,0")
+		 (match_operand:HI 2 "general_operand" "N,i,I,umi*A*d,!*d*w")))]
   "TARGET_M6811"
   "*
 {
@@ -3924,7 +3924,7 @@
 (define_insn "*ashlhi3_2"
   [(set (match_operand:HI 0 "register_operand" "=d")
 	(ashift:HI (match_operand:HI 1 "register_operand" "0")
-                   (match_operand:HI 2 "register_operand" "x")))
+                   (match_operand:HI 2 "register_operand" "+x")))
    (clobber (match_dup 2))]
   ""
   "*
@@ -3933,10 +3933,10 @@
   return \"bsr\\t___lshlhi3\";
 }")
 
-(define_insn ""
+(define_insn "*ashlhi3"
   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
 	(ashift:HI (match_dup 0)
-		   (match_operand:HI 1 "register_operand" "x")))
+		   (match_operand:HI 1 "register_operand" "+x")))
    (clobber (match_dup 1))]
   ""
   "*
@@ -4191,9 +4191,9 @@
       output_asm_insn (\"rolb\", operands);
       output_asm_insn (\"rola\", operands);
       output_asm_insn (\"tab\", operands);
-      output_asm_insn (\"anda\\t#1\", operands);
+      output_asm_insn (\"anda\\t#0\", operands);
       output_asm_insn (\"bcc\\t%l0\", ops);
-      output_asm_insn (\"oraa\\t#0xFE\", ops);
+      output_asm_insn (\"coma\", ops);
 
       ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
 				 CODE_LABEL_NUMBER (ops[0]));
@@ -4213,7 +4213,7 @@
 (define_insn "*ashrhi3"
   [(set (match_operand:HI 0 "register_operand" "=d,x")
 	(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
-	             (match_operand:HI 2 "register_operand" "x,d")))
+	             (match_operand:HI 2 "register_operand" "+x,+d")))
    (clobber (match_dup 2))]
   ""
   "*
@@ -4522,8 +4522,10 @@
 	             (const_int 16)))
    (clobber (match_scratch:HI 2 "=X,X,X,X"))]
    ""
-   "#
+   "@
+    #
     xgdx\\n\\tldx\\t#0
+    #
     #")
 
 (define_insn "*lshrsi3_const1"
@@ -4741,7 +4743,7 @@
 (define_insn "*lshrhi3"
   [(set (match_operand:HI 0 "register_operand" "=d,x")
 	(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0")
-		     (match_operand:HI 2 "register_operand" "x,d")))
+		     (match_operand:HI 2 "register_operand" "+x,+d")))
    (clobber (match_dup 2))]
   ""
   "*
@@ -5342,7 +5344,7 @@
 ;;
 ;;- Call a function that returns no value.
 (define_insn "call"
-  [(call (match_operand:QI 0 "memory_operand" "mAi")
+  [(call (match_operand:QI 0 "memory_operand" "m")
 	 (match_operand:SI 1 "general_operand" "g"))]
   ;; Operand 1 not really used on the m68hc11.
   ""
@@ -5363,7 +5365,7 @@
 
 (define_insn "call_value"
   [(set (match_operand 0 "" "=g")
-	(call (match_operand:QI 1 "general_operand" "mAi")
+	(call (match_operand:QI 1 "memory_operand" "m")
 	      (match_operand:SI 2 "general_operand" "g")))]
   ""
  "*