2nd try for patch for automaton based pipeline hazard recognizer (part #1)

[Neil Booth]

Hi Vladimir,

Vladimir Makarov wrote:-

> ! To achieve better productivity the most of modern processors

s/the most of/most/

> ! (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
> ! processors) have many @dfn{functional units} on which several
> ! instructions can be executed simultaneously.  An instruction execution
> ! can be started only if its issue conditions are satisfied.  If not,

s/execution can be started only if/only starts execution if/

> ! There are two major kinds of interlock delays in modern processors.
> ! The first one is a data dependence delay determining @dfn{instruction
> ! latency time}.  The instruction execution is not started until all
> ! source data have been evaluated by the previous instructions (there

s/the previous/prior/

In fact, this is not efficient.  If and when your patch is approved,
commit the documentation as you have it, let me know, and I'll go
through and touch up the English.

Thanks!

Neil.