SH4 ic_cache_invalidate code broken

[Toshi Morita]

> On Jun  4, 2001, Toshi Morita <tm2@best.com> wrote:
> 
> >> Index: gcc/ChangeLog
> >> from  Alexandre Oliva  <aoliva@redhat.com>
> >> 
> >> * config/sh/lib1funcs.asm (ic_invalidate): Align the
> >> cache-mirroring sequence.  Add nops.
> 
> > This code makes an implicit assumption that the thunk fits in 
> > exactly one cache line. Is this assumption correct?
> 
> According to the SH4 manual, yes.
> 
> -- 
> Alexandre Oliva   Enjoy Guarana', see http://www.ic.unicamp.br/~oliva/
> Red Hat GCC Developer                  aoliva@{cygnus.com, redhat.com}
> CS PhD student at IC-Unicamp        oliva@{lsd.ic.unicamp.br, gnu.org}
> Free Software Evangelist    *Please* write to mailing lists, not to me
> 

I'd like a bit more information on this...
What is the size and alignment of the thunk?

I just thought of another failure mode for this code chunk.
It assumes that both ic_invalidate and the target thunk are
in the cacheable area.

If ic_invalidate is in the noncacheable area, then it will NOT
clear any cache lines.

I think, at the very minimum, these assumptions need to be
documented in comments so people will be less likely to trip
over them.

It'd be nice if we could also generate a real hardware
cache clear (set ICI of the CCR) depending on if a define
is set, maybe something like HARDWARE_CACHE_CLEAR.
That way, the user can choose whether to use a fast
software line clear or a slow invalidate of the entire
instruction cache.

Toshi