IA64 HP-UX ILP32 mode patch

[Richard Henderson]

On Mon, Jul 16, 2001 at 02:08:09PM -0700, Steve Ellcey wrote:
> I created an instruction for this that I called extend_ptr ...

FWIW, I'd rather this be called ptr_extend, to match
sign_extend and zero_extend.

> I also created a new macro, MD_CONVERT_MEMORY_ADDRESS.  Unfortunately,
> no matter how hard I tried I could not get convert_memory_address to
> work for me as it was written.

I see two changes in your version.  One, you check cfun nonnull,
which seems pointless to me -- why wouldn't we have run into this
on other targets?  Two, you remove support for CONST, PLUS, and MULT.
What examples lead you to this?  If it's really unavoidable, perhaps
you should simply add POINTERS_EXTEND_UNSIGNED >= 0 to this cases.

I really don't want another hook here.

> + (define_insn "extend_ptr"
> +   [(set (match_operand:DI 0 "register_operand" "=r")
> +         (unspec:DI [(match_operand:SI 1 "register_operand" "r")] 24))]
> +   ""
> +   "addp4 %0 = 0,%1"
> +   [(set_attr "type" "I")])

Use gr_register_operand, not register_operand.

This would have been type "A", not "I", and anyway these have
all been changed to (set_attr "itanium_class" "ialu").

You probably also want

  (define_insn "*ptr_extend_plus"
    [(set (match_operand:DI 0 "gr_register_operand" "=r")
	  (unspec:DI
	   [(plus:SI (match_operand:SI 1 "gr_register_operand" "%r")
		     (match_operand:SI 2 "gr_reg_or_14bit_operand" "rI"))]
	   24))]
    ""
    "addp4 %0 = %2, %1"
    [(set_attr "itanium_class" "ialu")])

  (define_insn "*ptr_extend_shl"
    [(set (match_operand:DI 0 "gr_register_operand" "=r")
	  (unspec:DI
	   [(ashift:SI (match_operand:SI 1 "gr_register_operand" "r")
		       (match_operand:SI 2 "const_int_operand" "n"))]
	   24))]
    "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 4"
    "shladdp4 %0 = %1, %2, r0"
    [(set_attr "itanium_class" "ialu")])

  (define_insn "*ptr_extend_shladd"
    [(set (match_operand:DI 0 "gr_register_operand" "=r")
	  (unspec:DI
	   [(plus:SI (mult:SI (match_operand:SI 1 "gr_register_operand" "r")
			      (match_operand:SI 2 "shladd_operand" "n"))
		     (match_operand:SI 3 "gr_register_operand" "r"))]
	   24))]
    ""
    "shladdp4 %0 = %1, %S2, %3"
    [(set_attr "itanium_class" "ialu")])


r~