sparc to bootstrapland
Jan Hubicka
jh@suse.cz
Mon Jul 9 11:45:00 GMT 2001
Hi,
Sparc backend calls gen_highpart on VOIDmode constants, that is not well
defined operation. To fix it I've introduced gen_highpart_mode accepting
extra operand with proper mode of operand.
I am just finishing stage2 of sparc bootstrap; previously it failed stage1.
OK to install assuming that bootstrap complettes?
Honza
Mon Jul 9 20:41:41 CEST 2001 Jan Hubicka <jh@suse.cz>
* emit-rtl.c (gen_highpart_mode): New.
* rtl.h (gen_highpart_mode): Declare.
* sparc.md (insn splitters): Use gen_highpart_mode, whenever the
operand can be VOIDmode constant.
Index: emit-rtl.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/emit-rtl.c,v
retrieving revision 1.187
diff -c -3 -p -r1.187 emit-rtl.c
*** emit-rtl.c 2001/07/09 11:20:48 1.187
--- emit-rtl.c 2001/07/09 18:41:19
*************** gen_highpart (mode, x)
*** 1146,1151 ****
--- 1146,1168 ----
abort ();
return result;
}
+
+ /* Like gen_highpart_mode, but accept mode of EXP operand in case EXP can
+ be VOIDmode constant. */
+ rtx
+ gen_highpart_mode (outermode, innermode, exp)
+ enum machine_mode outermode, innermode;
+ rtx exp;
+ {
+ if (GET_MODE (exp) != VOIDmode)
+ {
+ if (GET_MODE (exp) != innermode)
+ abort ();
+ return gen_highpart (outermode, exp);
+ }
+ return simplify_gen_subreg (outermode, exp, innermode,
+ subreg_highpart_offset (outermode, innermode));
+ }
/* Return offset in bytes to get OUTERMODE low part
of the value in mode INNERMODE stored in memory in target format. */
Index: rtl.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/rtl.h,v
retrieving revision 1.268
diff -c -3 -p -r1.268 rtl.h
*** rtl.h 2001/07/03 19:44:06 1.268
--- rtl.h 2001/07/09 18:41:20
*************** extern rtx gen_lowpart_if_possible PARAM
*** 1190,1195 ****
--- 1190,1197 ----
/* In emit-rtl.c */
extern rtx gen_highpart PARAMS ((enum machine_mode, rtx));
+ extern rtx gen_highpart_mode PARAMS ((enum machine_mode,
+ enum machine_mode, rtx));
extern rtx gen_realpart PARAMS ((enum machine_mode, rtx));
extern rtx gen_imagpart PARAMS ((enum machine_mode, rtx));
extern rtx operand_subword PARAMS ((rtx, unsigned int, int,
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/sparc/sparc.md,v
retrieving revision 1.126
diff -c -3 -p -r1.126 sparc.md
*** sparc.md 2001/07/03 01:58:35 1.126
--- sparc.md 2001/07/09 18:41:24
***************
*** 5633,5639 ****
operands[4] = gen_lowpart (SImode, operands[1]);
operands[5] = gen_lowpart (SImode, operands[2]);
operands[6] = gen_highpart (SImode, operands[0]);
! operands[7] = gen_highpart (SImode, operands[1]);
#if HOST_BITS_PER_WIDE_INT == 32
if (GET_CODE (operands[2]) == CONST_INT)
{
--- 5633,5639 ----
operands[4] = gen_lowpart (SImode, operands[1]);
operands[5] = gen_lowpart (SImode, operands[2]);
operands[6] = gen_highpart (SImode, operands[0]);
! operands[7] = gen_highpart_mode (SImode, DImode, operands[1]);
#if HOST_BITS_PER_WIDE_INT == 32
if (GET_CODE (operands[2]) == CONST_INT)
{
***************
*** 5644,5650 ****
}
else
#endif
! operands[8] = gen_highpart (SImode, operands[2]);
}")
(define_split
--- 5644,5650 ----
}
else
#endif
! operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
}")
(define_split
***************
*** 5680,5686 ****
}
else
#endif
! operands[8] = gen_highpart (SImode, operands[2]);
}")
;; LTU here means "carry set"
--- 5680,5686 ----
}
else
#endif
! operands[8] = gen_highpart_mode (SImode, DImode, operands[2]);
}")
;; LTU here means "carry set"
***************
*** 5714,5720 ****
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))
(set (match_dup 4) (const_int 0))]
"operands[3] = gen_lowpart (SImode, operands[0]);
! operands[4] = gen_highpart (SImode, operands[1]);")
(define_insn "*addx_extend_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
--- 5714,5720 ----
(ltu:SI (reg:CC_NOOV 100) (const_int 0))))
(set (match_dup 4) (const_int 0))]
"operands[3] = gen_lowpart (SImode, operands[0]);
! operands[4] = gen_highpart_mode (SImode, DImode, operands[1]);")
(define_insn "*addx_extend_sp64"
[(set (match_operand:DI 0 "register_operand" "=r")
***************
*** 5929,5935 ****
{
rtx highp, lowp;
! highp = gen_highpart (SImode, operands[2]);
lowp = gen_lowpart (SImode, operands[2]);
if ((lowp == const0_rtx)
&& (operands[0] == operands[1]))
--- 5929,5935 ----
{
rtx highp, lowp;
! highp = gen_highpart_mode (SImode, DImode, operands[2]);
lowp = gen_lowpart (SImode, operands[2]);
if ((lowp == const0_rtx)
&& (operands[0] == operands[1]))
***************
*** 5937,5943 ****
emit_insn (gen_rtx_SET (VOIDmode,
gen_highpart (SImode, operands[0]),
gen_rtx_MINUS (SImode,
! gen_highpart (SImode, operands[1]),
highp)));
}
else
--- 5937,5944 ----
emit_insn (gen_rtx_SET (VOIDmode,
gen_highpart (SImode, operands[0]),
gen_rtx_MINUS (SImode,
! gen_highpart_mode (SImode, DImode,
! operands[1]),
highp)));
}
else
***************
*** 5946,5952 ****
gen_lowpart (SImode, operands[1]),
lowp));
emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
! gen_highpart (SImode, operands[1]),
highp));
}
DONE;
--- 5947,5953 ----
gen_lowpart (SImode, operands[1]),
lowp));
emit_insn (gen_subx (gen_highpart (SImode, operands[0]),
! gen_highpart_mode (SImode, DImode, operands[1]),
highp));
}
DONE;
***************
*** 6800,6806 ****
}
else
#endif
! operands[8] = gen_highpart (SImode, operands[3]);
operands[9] = gen_lowpart (SImode, operands[3]);
}")
--- 6801,6807 ----
}
else
#endif
! operands[8] = gen_highpart_mode (SImode, DImode, operands[3]);
operands[9] = gen_lowpart (SImode, operands[3]);
}")
More information about the Gcc-patches
mailing list