patch for -msse-math
Jan Hubicka
jh@suse.cz
Tue Dec 11 10:34:00 GMT 2001
Hi
this patch adds -msse-math controlling whether sse will be used for for FP
arithmetics. The patch has passed bootstrap/regtesting and I've tested that
the various combinations of switches apepars to work properly.
Without the regclass propagation patches we will probably need to tweek
regalloc order to prioritize x87 over SSE regsiters when fp is not desirable,
but I will benchmark that first.
Honza
Tue Dec 11 19:22:21 CET 2001 Jan Hubicka <jh@suse.cz>
* i386.c (override_options): MASK_SSE_MATH defaults MASK_SSE.
(ix86_expand_fp_movcc): Use TARGET_SSE_MATH.
* i386.h (MASK_SSE_MATH): New.
(TARGET_SSE_MATH): New macro.
(TARGET_SWITCHES): Add sse-math.
* i386.md (swapsf): Fix condition.
(add?f, sub?f, mul?f, div?f, sqrt?f, min?f): Use TARGET_SSE_MATH.
(fp_?f_*_nosse): New.
(fp_*): Use TARGET_SSE_MATH.
* invoke.texi (-msse-math): Document.
Index: i386.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.c,v
retrieving revision 1.343
diff -c -3 -p -r1.343 i386.c
*** i386.c 2001/12/09 20:13:08 1.343
--- i386.c 2001/12/11 18:21:54
*************** override_options ()
*** 1027,1037 ****
if (TARGET_RTD)
error ("-mrtd calling convention not supported in the 64bit mode");
/* Enable by default the SSE and MMX builtins. */
! target_flags |= MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE;
}
/* It makes no sense to ask for just SSE builtins, so MMX is also turned
on by -msse. */
if (TARGET_SSE)
target_flags |= MASK_MMX;
--- 1027,1040 ----
if (TARGET_RTD)
error ("-mrtd calling convention not supported in the 64bit mode");
/* Enable by default the SSE and MMX builtins. */
! target_flags |= (MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE
! | MASK_SSE_MATH);
}
/* It makes no sense to ask for just SSE builtins, so MMX is also turned
on by -msse. */
+ if (TARGET_SSE_MATH)
+ target_flags |= MASK_SSE;
if (TARGET_SSE)
target_flags |= MASK_MMX;
*************** ix86_expand_fp_movcc (operands)
*** 8078,8085 ****
/* For SF/DFmode conditional moves based on comparisons
in same mode, we may want to use SSE min/max instructions. */
! if (((TARGET_SSE && GET_MODE (operands[0]) == SFmode)
! || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))
&& GET_MODE (ix86_compare_op0) == GET_MODE (operands[0])
/* The SSE comparisons does not support the LTGT/UNEQ pair. */
&& (!TARGET_IEEE_FP
--- 8081,8088 ----
/* For SF/DFmode conditional moves based on comparisons
in same mode, we may want to use SSE min/max instructions. */
! if (((TARGET_SSE_MATH && GET_MODE (operands[0]) == SFmode)
! || (TARGET_SSE2 && TARGET_SSE_MATH && GET_MODE (operands[0]) == DFmode))
&& GET_MODE (ix86_compare_op0) == GET_MODE (operands[0])
/* The SSE comparisons does not support the LTGT/UNEQ pair. */
&& (!TARGET_IEEE_FP
Index: i386.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.h,v
retrieving revision 1.221
diff -c -3 -p -r1.221 i386.h
*** i386.h 2001/12/09 20:13:11 1.221
--- i386.h 2001/12/11 18:21:55
*************** extern int target_flags;
*** 126,131 ****
--- 126,132 ----
#define MASK_MIX_SSE_I387 0x00800000 /* Mix SSE and i387 instructions */
#define MASK_64BIT 0x01000000 /* Produce 64bit code */
#define MASK_NO_RED_ZONE 0x02000000 /* Do not use red zone */
+ #define MASK_SSE_MATH 0x04000000 /* Use SSE(2) for fp arithmetic */
/* Temporary codegen switches */
#define MASK_INTEL_SYNTAX 0x00000200
*************** extern const int x86_epilogue_using_move
*** 267,272 ****
--- 268,274 ----
#define TARGET_SSE ((target_flags & (MASK_SSE | MASK_SSE2)) != 0)
#define TARGET_SSE2 ((target_flags & MASK_SSE2) != 0)
+ #define TARGET_SSE_MATH ((target_flags & (MASK_SSE_MATH)) != 0)
#define TARGET_MIX_SSE_I387 ((target_flags & MASK_MIX_SSE_I387) != 0)
#define TARGET_MMX ((target_flags & MASK_MMX) != 0)
#define TARGET_3DNOW ((target_flags & MASK_3DNOW) != 0)
*************** extern const int x86_epilogue_using_move
*** 350,355 ****
--- 352,361 ----
N_("Support MMX and SSE builtins and code generation") }, \
{ "no-sse", -MASK_SSE, \
N_("Do not support MMX and SSE builtins and code generation") }, \
+ { "sse-math", MASK_SSE_MATH, \
+ N_("Use SSE(2) for scalar floating point arithmetic") }, \
+ { "no-sse-math", -MASK_SSE_MATH, \
+ N_("Do not use SSE(2) for scalar floating point arithmetic") }, \
{ "sse2", MASK_SSE2, \
N_("Support MMX, SSE and SSE2 builtins and code generation") }, \
{ "no-sse2", -MASK_SSE2, \
Index: i386.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/i386/i386.md,v
retrieving revision 1.321
diff -c -3 -p -r1.321 i386.md
*** i386.md 2001/12/10 14:30:11 1.321
--- i386.md 2001/12/11 18:21:59
***************
*** 2776,2782 ****
(match_operand:SF 1 "register_operand" "+f"))
(set (match_dup 1)
(match_dup 0))]
! "reload_completed || !TARGET_SSE2"
{
if (STACK_TOP_P (operands[0]))
return "fxch\t%1";
--- 2776,2782 ----
(match_operand:SF 1 "register_operand" "+f"))
(set (match_dup 1)
(match_dup 0))]
! "reload_completed || !TARGET_SSE"
{
if (STACK_TOP_P (operands[0]))
return "fxch\t%1";
***************
*** 6890,6903 ****
[(set (match_operand:DF 0 "register_operand" "")
(plus:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE2"
"")
(define_expand "addsf3"
[(set (match_operand:SF 0 "register_operand" "")
(plus:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE"
"")
;; Subtract instructions
--- 6890,6903 ----
[(set (match_operand:DF 0 "register_operand" "")
(plus:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "addsf3"
[(set (match_operand:SF 0 "register_operand" "")
(plus:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Subtract instructions
***************
*** 7207,7220 ****
[(set (match_operand:DF 0 "register_operand" "")
(minus:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE2"
"")
(define_expand "subsf3"
[(set (match_operand:SF 0 "register_operand" "")
(minus:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE"
"")
;; Multiply instructions
--- 7207,7220 ----
[(set (match_operand:DF 0 "register_operand" "")
(minus:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "subsf3"
[(set (match_operand:SF 0 "register_operand" "")
(minus:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Multiply instructions
***************
*** 7533,7546 ****
[(set (match_operand:DF 0 "register_operand" "")
(mult:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE2"
"")
(define_expand "mulsf3"
[(set (match_operand:SF 0 "register_operand" "")
(mult:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE"
"")
;; Divide instructions
--- 7533,7546 ----
[(set (match_operand:DF 0 "register_operand" "")
(mult:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "mulsf3"
[(set (match_operand:SF 0 "register_operand" "")
(mult:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Divide instructions
***************
*** 7587,7600 ****
[(set (match_operand:DF 0 "register_operand" "")
(div:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE2"
"")
(define_expand "divsf3"
[(set (match_operand:SF 0 "register_operand" "")
(div:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE"
"")
;; Remainder instructions.
--- 7587,7600 ----
[(set (match_operand:DF 0 "register_operand" "")
(div:DF (match_operand:DF 1 "register_operand" "")
(match_operand:DF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
"")
(define_expand "divsf3"
[(set (match_operand:SF 0 "register_operand" "")
(div:SF (match_operand:SF 1 "register_operand" "")
(match_operand:SF 2 "nonimmediate_operand" "")))]
! "TARGET_80387 || TARGET_SSE_MATH"
"")
;; Remainder instructions.
***************
*** 13849,13860 ****
;; Gcc is slightly more smart about handling normal two address instructions
;; so use special patterns for add and mull.
(define_insn "*fop_sf_comm"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "%0,0")
(match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
! "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
--- 13849,13874 ----
;; Gcc is slightly more smart about handling normal two address instructions
;; so use special patterns for add and mull.
+ (define_insn "*fop_sf_comm_nosse"
+ [(set (match_operand:SF 0 "register_operand" "=f")
+ (match_operator:SF 3 "binary_fp_operator"
+ [(match_operand:SF 1 "register_operand" "%0")
+ (match_operand:SF 2 "nonimmediate_operand" "fm")]))]
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop")))
+ (set_attr "mode" "SF")])
+
(define_insn "*fop_sf_comm"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "%0,0")
(match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
! "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
***************
*** 13870,13886 ****
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "%0")
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
! "TARGET_SSE && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
(define_insn "*fop_df_comm"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "%0,0")
(match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
! "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
--- 13884,13914 ----
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "%0")
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
! "TARGET_SSE_MATH && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
(set_attr "mode" "SF")])
+ (define_insn "*fop_df_comm_nosse"
+ [(set (match_operand:DF 0 "register_operand" "=f")
+ (match_operator:DF 3 "binary_fp_operator"
+ [(match_operand:DF 1 "register_operand" "%0")
+ (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
+ "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+ && GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (if_then_else (match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (const_string "fop")))
+ (set_attr "mode" "DF")])
+
(define_insn "*fop_df_comm"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "%0,0")
(match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
! "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
***************
*** 13896,13902 ****
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "%0")
(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
! "TARGET_SSE2
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
--- 13924,13930 ----
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "%0")
(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
! "TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) == 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
***************
*** 13929,13940 ****
(const_string "fop")))
(set_attr "mode" "XF")])
(define_insn "*fop_sf_1"
[(set (match_operand:SF 0 "register_operand" "=f,f,x")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
! "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
--- 13957,13986 ----
(const_string "fop")))
(set_attr "mode" "XF")])
+ (define_insn "*fop_sf_1_nosse"
+ [(set (match_operand:SF 0 "register_operand" "=f,f")
+ (match_operator:SF 3 "binary_fp_operator"
+ [(match_operand:SF 1 "nonimmediate_operand" "0,fm")
+ (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))]
+ "TARGET_80387 && !TARGET_SSE_MATH
+ && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(match_operand:SF 3 "mult_operator" "")
+ (const_string "fmul")
+ (match_operand:SF 3 "div_operator" "")
+ (const_string "fdiv")
+ ]
+ (const_string "fop")))
+ (set_attr "mode" "SF")])
+
(define_insn "*fop_sf_1"
[(set (match_operand:SF 0 "register_operand" "=f,f,x")
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
! "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
***************
*** 13954,13960 ****
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0")
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
! "TARGET_SSE
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
--- 14000,14006 ----
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0")
(match_operand:SF 2 "nonimmediate_operand" "xm")]))]
! "TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")
***************
*** 13966,13972 ****
(match_operator:SF 3 "binary_fp_operator"
[(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:SF 2 "register_operand" "0,0")]))]
! "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
--- 14012,14018 ----
(match_operator:SF 3 "binary_fp_operator"
[(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:SF 2 "register_operand" "0,0")]))]
! "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
***************
*** 13984,13990 ****
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0,0")
(float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
! "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
--- 14030,14036 ----
(match_operator:SF 3 "binary_fp_operator"
[(match_operand:SF 1 "register_operand" "0,0")
(float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
! "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:SF 3 "mult_operator" "")
***************
*** 13997,14008 ****
(set_attr "ppro_uops" "many")
(set_attr "mode" "SI")])
(define_insn "*fop_df_1"
[(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
! "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
--- 14043,14073 ----
(set_attr "ppro_uops" "many")
(set_attr "mode" "SI")])
+ (define_insn "*fop_df_1_nosse"
+ [(set (match_operand:DF 0 "register_operand" "=f,f")
+ (match_operator:DF 3 "binary_fp_operator"
+ [(match_operand:DF 1 "nonimmediate_operand" "0,fm")
+ (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
+ "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+ && GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
+ && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+ "* return output_387_binary_op (insn, operands);"
+ [(set (attr "type")
+ (cond [(match_operand:DF 3 "mult_operator" "")
+ (const_string "fmul")
+ (match_operand:DF 3 "div_operator" "")
+ (const_string "fdiv")
+ ]
+ (const_string "fop")))
+ (set_attr "mode" "DF")])
+
+
(define_insn "*fop_df_1"
[(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
(match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
! "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'
&& (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
"* return output_387_binary_op (insn, operands);"
***************
*** 14022,14028 ****
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0")
(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
! "TARGET_SSE
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")])
--- 14087,14093 ----
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0")
(match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
! "TARGET_SSE2 && TARGET_SSE_MATH
&& GET_RTX_CLASS (GET_CODE (operands[3])) != 'c'"
"* return output_387_binary_op (insn, operands);"
[(set_attr "type" "sse")])
***************
*** 14033,14039 ****
(match_operator:DF 3 "binary_fp_operator"
[(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:DF 2 "register_operand" "0,0")]))]
! "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
--- 14098,14104 ----
(match_operator:DF 3 "binary_fp_operator"
[(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
(match_operand:DF 2 "register_operand" "0,0")]))]
! "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
***************
*** 14051,14057 ****
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0,0")
(float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
! "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE2"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
--- 14116,14122 ----
(match_operator:DF 3 "binary_fp_operator"
[(match_operand:DF 1 "register_operand" "0,0")
(float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
! "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
***************
*** 14087,14093 ****
[(match_operand:DF 1 "register_operand" "0,f")
(float_extend:DF
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
! "TARGET_80387 && !TARGET_SSE2"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
--- 14152,14158 ----
[(match_operand:DF 1 "register_operand" "0,f")
(float_extend:DF
(match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
! "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "mult_operator" "")
***************
*** 14421,14429 ****
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
! "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE2"
{
! if (!TARGET_SSE2)
operands[1] = force_reg (DFmode, operands[1]);
})
--- 14486,14495 ----
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
! "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
! || (TARGET_SSE2 && TARGET_SSE_MATH)"
{
! if (!TARGET_SSE2 || !TARGET_SSE_MATH)
operands[1] = force_reg (DFmode, operands[1]);
})
***************
*** 14431,14437 ****
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (TARGET_SSE2 && TARGET_MIX_SSE_I387)"
"@
fsqrt
sqrtsd\t{%1, %0|%0, %1}"
--- 14497,14503 ----
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@
fsqrt
sqrtsd\t{%1, %0|%0, %1}"
***************
*** 14442,14448 ****
(define_insn "sqrtdf2_1_sse_only"
[(set (match_operand:DF 0 "register_operand" "=Y")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
! "TARGET_SSE2 && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
"sqrtsd\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")
--- 14508,14514 ----
(define_insn "sqrtdf2_1_sse_only"
[(set (match_operand:DF 0 "register_operand" "=Y")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
! "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
"sqrtsd\t{%1, %0|%0, %1}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")
***************
*** 14452,14458 ****
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (!TARGET_SSE2 && !TARGET_MIX_SSE_I387)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
--- 14518,14524 ----
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && (!TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
***************
*** 14462,14468 ****
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 && !TARGET_SSE2"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
--- 14528,14535 ----
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && !(TARGET_SSE2 && TARGET_SSE_MATH)"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")
***************
*** 15963,15969 ****
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))])]
! "TARGET_SSE2"
"#")
(define_insn "*mindf"
--- 16030,16036 ----
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))])]
! "TARGET_SSE2 && TARGET_SSE_MATH"
"#")
(define_insn "*mindf"
***************
*** 15973,15979 ****
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && TARGET_IEEE_FP"
"#")
(define_insn "*mindf_nonieee"
--- 16040,16046 ----
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
"#")
(define_insn "*mindf_nonieee"
***************
*** 15983,15989 ****
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && !TARGET_IEEE_FP"
"#")
(define_split
--- 16050,16056 ----
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
"#")
(define_split
***************
*** 16031,16037 ****
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
(match_dup 1)
(match_dup 2)))]
! "TARGET_SSE2 && reload_completed"
"minsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
--- 16098,16104 ----
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
(match_dup 1)
(match_dup 2)))]
! "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
"minsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
***************
*** 16124,16130 ****
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))])]
! "TARGET_SSE2"
"#")
(define_insn "*maxdf"
--- 16191,16197 ----
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))])]
! "TARGET_SSE2 && TARGET_SSE_MATH"
"#")
(define_insn "*maxdf"
***************
*** 16134,16140 ****
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && TARGET_IEEE_FP"
"#")
(define_insn "*maxdf_nonieee"
--- 16201,16207 ----
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP"
"#")
(define_insn "*maxdf_nonieee"
***************
*** 16144,16150 ****
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && !TARGET_IEEE_FP"
"#")
(define_split
--- 16211,16217 ----
(match_dup 1)
(match_dup 2)))
(clobber (reg:CC 17))]
! "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_IEEE_FP"
"#")
(define_split
***************
*** 16191,16197 ****
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
(match_dup 1)
(match_dup 2)))]
! "TARGET_SSE2 && reload_completed"
"maxsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
--- 16258,16264 ----
(match_operand:DF 2 "nonimmediate_operand" "Ym"))
(match_dup 1)
(match_dup 2)))]
! "TARGET_SSE2 && TARGET_SSE_MATH && reload_completed"
"maxsd\t{%2, %0|%0, %2}"
[(set_attr "type" "sse")
(set_attr "mode" "DF")])
Index: invoke.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/doc/invoke.texi,v
retrieving revision 1.88
diff -c -3 -p -r1.88 invoke.texi
*** invoke.texi 2001/12/10 03:27:49 1.88
--- invoke.texi 2001/12/11 18:33:31
*************** in the following sections.
*** 478,484 ****
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol
! -mmmx -msse -m3dnow @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
--- 478,484 ----
-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
-mno-wide-multiply -mrtd -malign-double @gol
-mpreferred-stack-boundary=@var{num} @gol
! -mmmx -msse -msse2 -msse-math -m3dnow @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
*************** preferred alignment to @option{-mpreferr
*** 7650,7655 ****
--- 7650,7657 ----
@itemx -mno-mmx
@item -msse
@itemx -mno-sse
+ @item -msse2
+ @itemx -mno-sse2
@item -m3dnow
@itemx -mno-3dnow
@opindex mmmx
*************** By default GCC inlines string operations
*** 8060,8065 ****
--- 8062,8076 ----
aligned at least to 4 byte boundary. This enables more inlining, increase code
size, but may improve performance of code that depends on fast memcpy, strlen
and memset for short lengths.
+
+ @item -msse-math
+ @opindex msse-math
+ Enable use of SSE instruction set for single precision fp arithmetics. In the
+ combination with @code{-msse2} double precision arithmetics will be done using
+ SSE instruction set too. This switch should increase performance of floating
+ point code on processors supporting the extension considerably, but results
+ are not equivalent to x87 floating point arithmtics as SSE register store
+ only 32 or 64bits of value, while x87 floating point registers store 80bits.
@item -momit-leaf-frame-pointer
@opindex momit-leaf-frame-pointer
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