A patch for dfa-branch
Vladimir Makarov
vmakarov@tooth.toronto.redhat.com
Fri Aug 31 07:19:00 GMT 2001
I've commited the following patch into dfa-branch.
2001-08-31 Vladimir Makarov <vmakarov@redhat.com>
* haifa-sched.c (insn_cost, schedule_insn, queue_to_ready,
schedule_block, sched_init, sched_finish): Add missed calls of
use_dfa_pipeline_interface.
* sched-rgn.c (init_ready_list, new_ready, debug_dependencies):
Ditto.
* sched-vis.c (get_visual_tbl_length): Ditto.
Index: haifa-sched.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/haifa-sched.c,v
retrieving revision 1.185
diff -c -p -r1.185 haifa-sched.c
*** haifa-sched.c 2001/08/27 18:13:38 1.185
--- haifa-sched.c 2001/08/31 13:13:56
*************** insn_cost (insn, link, used)
*** 732,738 ****
}
else
{
! if (targetm.sched.use_dfa_pipeline_interface)
cost = insn_default_latency (insn);
else
cost = result_ready_cost (insn);
--- 732,739 ----
}
else
{
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
cost = insn_default_latency (insn);
else
cost = result_ready_cost (insn);
*************** insn_cost (insn, link, used)
*** 755,761 ****
cost = 0;
else
{
! if (targetm.sched.use_dfa_pipeline_interface)
{
if (INSN_CODE (insn) >= 0)
{
--- 756,763 ----
cost = 0;
else
{
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
if (INSN_CODE (insn) >= 0)
{
*************** schedule_insn (insn, ready, clock)
*** 1096,1108 ****
rtx link;
int unit = 0;
! if (!targetm.sched.use_dfa_pipeline_interface)
unit = insn_unit (insn);
if (sched_verbose >= 2)
{
! if (targetm.sched.use_dfa_pipeline_interface)
{
fprintf (sched_dump,
";;\t\t--> scheduling insn <<<%d>>>:reservation ",
--- 1098,1112 ----
rtx link;
int unit = 0;
! if (!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
unit = insn_unit (insn);
if (sched_verbose >= 2)
{
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
fprintf (sched_dump,
";;\t\t--> scheduling insn <<<%d>>>:reservation ",
*************** schedule_insn (insn, ready, clock)
*** 1123,1129 ****
fprintf (sched_dump, "\n");
}
! if (!targetm.sched.use_dfa_pipeline_interface)
{
if (sched_verbose && unit == -1)
visualize_no_unit (insn);
--- 1127,1134 ----
fprintf (sched_dump, "\n");
}
! if (!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
{
if (sched_verbose && unit == -1)
visualize_no_unit (insn);
*************** queue_to_ready (ready)
*** 1625,1631 ****
insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
/* Advance time on one cycle. */
! if (targetm.sched.use_dfa_pipeline_interface)
{
if (targetm.sched.dfa_pre_cycle_insn)
state_transition (curr_state,
--- 1630,1637 ----
insn_queue[NEXT_Q_AFTER (q_ptr, stalls)] = 0;
/* Advance time on one cycle. */
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
if (targetm.sched.dfa_pre_cycle_insn)
state_transition (curr_state,
*************** queue_to_ready (ready)
*** 1643,1649 ****
}
}
! if (!targetm.sched.use_dfa_pipeline_interface && sched_verbose && stalls)
visualize_stall_cycles (stalls);
q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
--- 1649,1657 ----
}
}
! if ((!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
! && sched_verbose && stalls)
visualize_stall_cycles (stalls);
q_ptr = NEXT_Q_AFTER (q_ptr, stalls);
*************** schedule_block (b, rgn_n_insns)
*** 1932,1938 ****
init_block_visualization ();
}
! if (targetm.sched.use_dfa_pipeline_interface)
state_reset (curr_state);
else
clear_units ();
--- 1940,1947 ----
init_block_visualization ();
}
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
state_reset (curr_state);
else
clear_units ();
*************** schedule_block (b, rgn_n_insns)
*** 1943,1949 ****
ready.vec = (rtx *) xmalloc (ready.veclen * sizeof (rtx));
ready.n_ready = 0;
! if (targetm.sched.use_dfa_pipeline_interface)
{
/* It is used for first cycle multipass scheduling. */
temp_state = alloca (dfa_state_size);
--- 1952,1959 ----
ready.vec = (rtx *) xmalloc (ready.veclen * sizeof (rtx));
ready.n_ready = 0;
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
/* It is used for first cycle multipass scheduling. */
temp_state = alloca (dfa_state_size);
*************** schedule_block (b, rgn_n_insns)
*** 1964,1970 ****
q_ptr = 0;
q_size = 0;
! if (!targetm.sched.use_dfa_pipeline_interface)
max_insn_queue_index_macro_value = INSN_QUEUE_SIZE - 1;
else
max_insn_queue_index_macro_value = max_insn_queue_index;
--- 1974,1981 ----
q_ptr = 0;
q_size = 0;
! if (!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
max_insn_queue_index_macro_value = INSN_QUEUE_SIZE - 1;
else
max_insn_queue_index_macro_value = max_insn_queue_index;
*************** schedule_block (b, rgn_n_insns)
*** 1984,1990 ****
{
clock_var++;
! if (targetm.sched.use_dfa_pipeline_interface)
{
if (targetm.sched.dfa_pre_cycle_insn)
state_transition (curr_state,
--- 1995,2002 ----
{
clock_var++;
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
if (targetm.sched.dfa_pre_cycle_insn)
state_transition (curr_state,
*************** schedule_block (b, rgn_n_insns)
*** 2042,2048 ****
debug_ready_list (&ready);
}
! if (!targetm.sched.use_dfa_pipeline_interface)
{
if (ready.n_ready == 0 || !can_issue_more
|| !(*current_sched_info->schedule_more_p) ())
--- 2054,2061 ----
debug_ready_list (&ready);
}
! if (!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
{
if (ready.n_ready == 0 || !can_issue_more
|| !(*current_sched_info->schedule_more_p) ())
*************** schedule_block (b, rgn_n_insns)
*** 2183,2189 ****
}
}
! if (!targetm.sched.use_dfa_pipeline_interface && sched_verbose)
/* Debug info. */
visualize_scheduled_insns (clock_var);
}
--- 2196,2204 ----
}
}
! if ((!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
! && sched_verbose)
/* Debug info. */
visualize_scheduled_insns (clock_var);
}
*************** schedule_block (b, rgn_n_insns)
*** 2196,2202 ****
{
fprintf (sched_dump, ";;\tReady list (final): ");
debug_ready_list (&ready);
! if (!targetm.sched.use_dfa_pipeline_interface)
print_block_visualization ("");
}
--- 2211,2218 ----
{
fprintf (sched_dump, ";;\tReady list (final): ");
debug_ready_list (&ready);
! if (!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
print_block_visualization ("");
}
*************** schedule_block (b, rgn_n_insns)
*** 2243,2249 ****
free (ready.vec);
! if (targetm.sched.use_dfa_pipeline_interface)
free (ready_try);
}
--- 2259,2266 ----
free (ready.vec);
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
free (ready_try);
}
*************** sched_init (dump_file)
*** 2317,2323 ****
for (i = 0; i < old_max_uid; i++)
h_i_d [i].cost = -1;
! if (targetm.sched.use_dfa_pipeline_interface)
{
if (targetm.sched.init_dfa_pre_cycle_insn)
(*targetm.sched.init_dfa_pre_cycle_insn) ();
--- 2334,2341 ----
for (i = 0; i < old_max_uid; i++)
h_i_d [i].cost = -1;
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
if (targetm.sched.init_dfa_pre_cycle_insn)
(*targetm.sched.init_dfa_pre_cycle_insn) ();
*************** sched_init (dump_file)
*** 2391,2397 ****
}
}
! if (!targetm.sched.use_dfa_pipeline_interface && sched_verbose)
/* Find units used in this function, for visualization. */
init_target_units ();
--- 2409,2417 ----
}
}
! if ((!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
! && sched_verbose)
/* Find units used in this function, for visualization. */
init_target_units ();
*************** sched_finish ()
*** 2419,2425 ****
{
free (h_i_d);
! if (targetm.sched.use_dfa_pipeline_interface)
{
free (curr_state);
dfa_finish ();
--- 2439,2446 ----
{
free (h_i_d);
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
free (curr_state);
dfa_finish ();
Index: sched-rgn.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/sched-rgn.c,v
retrieving revision 1.15
diff -c -p -r1.15 sched-rgn.c
*** sched-rgn.c 2001/08/27 18:13:40 1.15
--- sched-rgn.c 2001/08/31 13:13:57
*************** init_ready_list (ready)
*** 2143,2155 ****
if (!CANT_MOVE (insn)
&& (!IS_SPECULATIVE_INSN (insn)
! || ((0
|| (targetm.sched.use_dfa_pipeline_interface
&& recog_memoized (insn) >= 0
&& min_insn_conflict_delay (curr_state, insn,
! insn) <= 3)
! || (!targetm.sched.use_dfa_pipeline_interface
! && insn_issue_delay (insn) <= 3))
&& check_live (insn, bb_src)
&& is_exception_free (insn, bb_src, target_bb))))
{
--- 2143,2156 ----
if (!CANT_MOVE (insn)
&& (!IS_SPECULATIVE_INSN (insn)
! || ((((!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
! && insn_issue_delay (insn) <= 3)
|| (targetm.sched.use_dfa_pipeline_interface
+ && (*targetm.sched.use_dfa_pipeline_interface) ()
&& recog_memoized (insn) >= 0
&& min_insn_conflict_delay (curr_state, insn,
! insn) <= 3))
&& check_live (insn, bb_src)
&& is_exception_free (insn, bb_src, target_bb))))
{
*************** new_ready (next)
*** 2259,2268 ****
|| (IS_SPECULATIVE_INSN (next)
&& (0
|| (targetm.sched.use_dfa_pipeline_interface
&& (recog_memoized (next) < 0
|| min_insn_conflict_delay (curr_state, next,
next) > 3))
! || (!targetm.sched.use_dfa_pipeline_interface
&& insn_issue_delay (next) > 3)
|| !check_live (next, INSN_BB (next))
|| !is_exception_free (next, INSN_BB (next), target_bb)))))
--- 2260,2271 ----
|| (IS_SPECULATIVE_INSN (next)
&& (0
|| (targetm.sched.use_dfa_pipeline_interface
+ && (*targetm.sched.use_dfa_pipeline_interface) ()
&& (recog_memoized (next) < 0
|| min_insn_conflict_delay (curr_state, next,
next) > 3))
! || ((!targetm.sched.use_dfa_pipeline_interface
! || !(*targetm.sched.use_dfa_pipeline_interface) ())
&& insn_issue_delay (next) > 3)
|| !check_live (next, INSN_BB (next))
|| !is_exception_free (next, INSN_BB (next), target_bb)))))
*************** debug_dependencies ()
*** 2655,2661 ****
fprintf (sched_dump, "\n;; --- Region Dependences --- b %d bb %d \n",
BB_TO_BLOCK (bb), bb);
! if (targetm.sched.use_dfa_pipeline_interface)
{
fprintf (sched_dump, ";; %7s%6s%6s%6s%6s%6s%14s\n",
"insn", "code", "bb", "dep", "prio", "cost",
--- 2658,2665 ----
fprintf (sched_dump, "\n;; --- Region Dependences --- b %d bb %d \n",
BB_TO_BLOCK (bb), bb);
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
fprintf (sched_dump, ";; %7s%6s%6s%6s%6s%6s%14s\n",
"insn", "code", "bb", "dep", "prio", "cost",
*************** debug_dependencies ()
*** 2694,2700 ****
continue;
}
! if (targetm.sched.use_dfa_pipeline_interface)
{
fprintf (sched_dump,
";; %s%5d%6d%6d%6d%6d%6d ",
--- 2698,2705 ----
continue;
}
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
fprintf (sched_dump,
";; %s%5d%6d%6d%6d%6d%6d ",
Index: sched-vis.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/sched-vis.c,v
retrieving revision 1.9
diff -c -p -r1.9 sched-vis.c
*** sched-vis.c 2001/08/27 18:13:40 1.9
--- sched-vis.c 2001/08/31 13:13:57
*************** get_visual_tbl_length ()
*** 124,130 ****
int n, n1;
char *s;
! if (targetm.sched.use_dfa_pipeline_interface)
{
visual_tbl_line_length = 1;
return 1; /* Can't return 0 because that will cause problems
--- 124,131 ----
int n, n1;
char *s;
! if (targetm.sched.use_dfa_pipeline_interface
! && (*targetm.sched.use_dfa_pipeline_interface) ())
{
visual_tbl_line_length = 1;
return 1; /* Can't return 0 because that will cause problems
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