New ia64 patterns for the combiner

[Bernd Schmidt]

This patch helps us turn

(p1) mov r1 = r2
(p2) mov r1 = r3
sub r4 = r4, r1

(which happens to occur in an important loop in SPEC95) into

(p1) sub r4 = r4, r2
(p2) sub r4 = r4, r3

Tested like the previous patches.


Bernd

        * config/ia64/ia64.c (condop_operator): New predicate.
        * config/ia64/ia64.h (PREDICATE_CODES): Add it.
        * config/ia64/ia64.md (cond_opsi2_internal and splitters): New
        patterns.

Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/ia64/ia64.c,v
retrieving revision 1.96
diff -u -p -r1.96 ia64.c
--- config/ia64/ia64.c	2001/05/22 20:10:18	1.96
+++ config/ia64/ia64.c	2001/08/05 09:46:18
@@ -694,6 +694,19 @@ predicate_operator (op, mode)
 	  && (code == EQ || code == NE));
 }

+/* Return 1 if this operator can be used in a conditional operation.  */
+
+int
+condop_operator (op, mode)
+    register rtx op;
+    enum machine_mode mode;
+{
+  enum rtx_code code = GET_CODE (op);
+  return ((GET_MODE (op) == mode || mode == VOIDmode)
+	  && (code == PLUS || code == MINUS || code == AND
+	      || code == IOR || code == XOR));
+}
+
 /* Return 1 if this is the ar.lc register.  */

 int
Index: config/ia64/ia64.h
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/ia64/ia64.h,v
retrieving revision 1.100
diff -u -p -r1.100 ia64.h
--- config/ia64/ia64.h	2001/05/15 01:31:32	1.100
+++ config/ia64/ia64.h	2001/08/05 09:46:18
@@ -2688,6 +2688,7 @@ do {									\
 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}},			\
 { "signed_inequality_operator", {GE, GT, LE, LT}},			\
 { "predicate_operator", {NE, EQ}},					\
+{ "condop_operator", {PLUS, MINUS, IOR, XOR, AND}},			\
 { "ar_lc_reg_operand", {REG}},						\
 { "ar_ccv_reg_operand", {REG}},						\
 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}},		\
Index: config/ia64/ia64.md
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/ia64/ia64.md,v
retrieving revision 1.99
diff -u -p -r1.99 ia64.md
--- config/ia64/ia64.md	2001/05/22 20:10:18	1.99
+++ config/ia64/ia64.md	2001/08/05 09:46:19
@@ -4468,6 +4478,82 @@
   "
 {
   operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? EQ : NE,
+				VOIDmode, operands[1], const0_rtx);
+}")
+
+(define_insn "*cond_opsi2_internal"
+  [(set (match_operand:SI 0 "gr_register_operand" "=r")
+	(match_operator:SI 5 "condop_operator"
+	  [(if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "c")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "r")
+	     (match_operand:SI 3 "gr_register_operand" "r"))
+	   (match_operand:SI 4 "gr_register_operand" "r")]))]
+  ""
+  "#"
+  [(set_attr "itanium_class" "ialu")
+   (set_attr "predicable" "no")])
+
+(define_split
+  [(set (match_operand:SI 0 "gr_register_operand" "")
+	(match_operator:SI 5 "condop_operator"
+	  [(if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "")
+	     (match_operand:SI 3 "gr_register_operand" ""))
+	   (match_operand:SI 4 "gr_register_operand" "")]))]
+  "reload_completed"
+  [(cond_exec
+     (match_dup 6)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 2) (match_dup 4)])))
+   (cond_exec
+     (match_dup 7)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 3) (match_dup 4)])))]
+  "
+{
+  operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
+				VOIDmode, operands[1], const0_rtx);
+}")
+
+(define_insn "*cond_opsi2_internal_b"
+  [(set (match_operand:SI 0 "gr_register_operand" "=r")
+	(match_operator:SI 5 "condop_operator"
+	  [(match_operand:SI 4 "gr_register_operand" "r")
+	   (if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "c")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "r")
+	     (match_operand:SI 3 "gr_register_operand" "r"))]))]
+  ""
+  "#"
+  [(set_attr "itanium_class" "ialu")
+   (set_attr "predicable" "no")])
+
+(define_split
+  [(set (match_operand:SI 0 "gr_register_operand" "")
+	(match_operator:SI 5 "condop_operator"
+	  [(match_operand:SI 4 "gr_register_operand" "")
+	   (if_then_else:SI
+	     (match_operator 6 "predicate_operator"
+	       [(match_operand:BI 1 "register_operand" "")
+	        (const_int 0)])
+	     (match_operand:SI 2 "gr_register_operand" "")
+	     (match_operand:SI 3 "gr_register_operand" ""))]))]
+  "reload_completed"
+  [(cond_exec
+     (match_dup 6)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 2)])))
+   (cond_exec
+     (match_dup 7)
+     (set (match_dup 0) (match_op_dup:SI 5 [(match_dup 4) (match_dup 3)])))]
+  "
+{
+  operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[6]) == NE ? EQ : NE,
 				VOIDmode, operands[1], const0_rtx);
 }")