regrename.c rewrite

Toon Moene
Sat Oct 28 13:05:00 GMT 2000

Richard Henderson wrote:

> Recently, David Mosberger and Hans Bohem at HP discovered that there
> is a poorly documented output dependancy stall on Itanium.  That is,
>         ld8     r14 = [r2] ;;
>         add     r14 = 1, r14 ;;
>         st8     [r2] = r14
> runs a couple of cycles slower than
>         ld8     r14 = [r2] ;;
>         add     r15 = 1, r14 ;;
>         st8     [r2] = r15
> So we are highly incented to get this pass fixed and possibly enabled
> by default at -ON for some N >= 2.

However, the sched2 pass still doesn't re-schedule the instructions
after they got the new (independent) registers assigned.

[ See my mail d.d. 11th of June this year: ]

This is a pretty important problem to solve; it only brings me 12 % in
the example given on the 21264, but that's because the 21264 is an OOO
CPU.  On an in-order CPU the gain should be far larger (yes, I know the
IA-64 has a different way of dealing with loop unrolling.  The example
uses loop unrolling because it is an easy way to expose the problem).

What's the way to attack this issue ?

Toon Moene - - phoneto: +31 346 214290
Saturnushof 14, 3738 XG  Maartensdijk, The Netherlands
GNU Fortran 77:
GNU Fortran 95: (under construction)

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