Run regrename by default at -O3

Richard Henderson rth@cygnus.com
Fri Oct 27 15:04:00 GMT 2000


This might generate some discussion:

Given that register renaming makes such a big difference on ia64,
it'd be kinda nice if it was enabled by default at high optimization.

However, the pass makes debugging basicly impossible, since local
variables move to a new home register basicly every time they are
used.  To my knowledge, *no* debugging format can express this.
Not even dwarf2.  And even if the debugging format could express
it, the compiler is certainly not set up to emit that sort of thing.

Based on that, I've chosen to enable it not at -O2, but at -O3.

Comments?


r~


PS: Oh, also run renaming before if-conversion, since renaming
won't be nearly as effective with a sequence of cond_exec insns.


        * invoke.texi: Document -frename-registers.  Add it to -O3.
        * toplev.c (rest_of_compilation): Run regrename before ifcvt2.
        (enum dump_file_index, dump_file): Update order.
        (main): Set flag_rename_registers at -O3.

Index: invoke.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/invoke.texi,v
retrieving revision 1.229
diff -c -p -d -r1.229 invoke.texi
*** invoke.texi	2000/10/25 17:45:41	1.229
--- invoke.texi	2000/10/27 21:44:54
*************** in the following sections.
*** 175,183 ****
  -fmove-all-movables  -fno-default-inline  -fno-defer-pop
  -fno-function-cse  -fno-inline  -fno-peephole -ftrapv
  -fomit-frame-pointer  -foptimize-register-moves -foptimize-sibling-calls
! -fregmove -frerun-cse-after-loop  -frerun-loop-opt  -freduce-all-givs
! -fschedule-insns  -fschedule-insns2  -fssa -fstrength-reduce
! -fstrict-aliasing  -fthread-jumps  -funroll-all-loops
  -funroll-loops 
  -O  -O0  -O1  -O2  -O3 -Os
  @end smallexample
--- 175,183 ----
  -fmove-all-movables  -fno-default-inline  -fno-defer-pop
  -fno-function-cse  -fno-inline  -fno-peephole -ftrapv
  -fomit-frame-pointer  -foptimize-register-moves -foptimize-sibling-calls
! -fregmove  -frename-registers  -frerun-cse-after-loop  -frerun-loop-opt
! -freduce-all-givs  -fschedule-insns  -fschedule-insns2  -fssa
! -fstrength-reduce  -fstrict-aliasing  -fthread-jumps  -funroll-all-loops
  -funroll-loops 
  -O  -O0  -O1  -O2  -O3 -Os
  @end smallexample
*************** perform loop unrolling or function inlin
*** 2577,2590 ****
  As compared to @samp{-O}, this option increases both compilation time
  and the performance of the generated code.
  
! @samp{-O2} turns on all optional optimizations except for loop unrolling
! and function inlining.  It also turns on the @samp{-fforce-mem} option
! on all machines and frame pointer elimination on machines where doing so
! does not interfere with debugging.
  
  @item -O3
  Optimize yet more.  @samp{-O3} turns on all optimizations specified by
! @samp{-O2} and also turns on the @samp{inline-functions} option.
  
  @item -O0
  Do not optimize.
--- 2577,2591 ----
  As compared to @samp{-O}, this option increases both compilation time
  and the performance of the generated code.
  
! @samp{-O2} turns on all optional optimizations except for loop unrolling,
! function inlining, and register renaming.  It also turns on the
! @samp{-fforce-mem} option on all machines and frame pointer elimination
! on machines where doing so does not interfere with debugging.
  
  @item -O3
  Optimize yet more.  @samp{-O3} turns on all optimizations specified by
! @samp{-O2} and also turns on the @samp{-finline-functions} and
! @samp{-frename-registers} options.
  
  @item -O0
  Do not optimize.
*************** halting the program may not work properl
*** 2805,2811 ****
  -fno-delete-null-pointer-checks to disable this optimizing for programs
  which depend on that behavior.
  
- 
  @item -fexpensive-optimizations
  Perform a number of minor optimizations that are relatively expensive.
  
--- 2806,2811 ----
*************** Perform dead-code elimination in SSA for
*** 3033,3038 ****
--- 3033,3044 ----
  Treat floating point constant as single precision constant instead of
  implicitly converting it to double precision constant.
  
+ @item -frename-registers
+ Attempt to avoid false dependancies in scheduled code by making use
+ of registers left over after register allocation.  This optimization
+ will most benefit processors with lots of registers.  It can, however,
+ make debugging impossible, since variables will no longer stay in
+ a ``home register''.
  @end table
  
  @node Preprocessor Options
Index: toplev.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/toplev.c,v
retrieving revision 1.390
diff -c -p -d -r1.390 toplev.c
*** toplev.c	2000/10/20 23:32:09	1.390
--- toplev.c	2000/10/27 21:44:54
*************** enum dump_file_index
*** 277,285 ****
    DFI_lreg,
    DFI_greg,
    DFI_flow2,
-   DFI_ce2,
    DFI_peephole2,
    DFI_rnreg,
    DFI_sched2,
    DFI_bbro,
    DFI_jump2,
--- 277,285 ----
    DFI_lreg,
    DFI_greg,
    DFI_flow2,
    DFI_peephole2,
    DFI_rnreg,
+   DFI_ce2,
    DFI_sched2,
    DFI_bbro,
    DFI_jump2,
*************** struct dump_file_info dump_file[DFI_MAX]
*** 321,329 ****
    { "lreg",	'l', 1, 0, 0 },
    { "greg",	'g', 1, 0, 0 },
    { "flow2",	'w', 1, 0, 0 },
-   { "ce2",	'E', 1, 0, 0 },
    { "peephole2", 'z', 1, 0, 0 },
    { "rnreg",	'n', 1, 0, 0 },
    { "sched2",	'R', 1, 0, 0 },
    { "bbro",	'B', 1, 0, 0 },
    { "jump2",	'J', 1, 0, 0 },
--- 321,329 ----
    { "lreg",	'l', 1, 0, 0 },
    { "greg",	'g', 1, 0, 0 },
    { "flow2",	'w', 1, 0, 0 },
    { "peephole2", 'z', 1, 0, 0 },
    { "rnreg",	'n', 1, 0, 0 },
+   { "ce2",	'E', 1, 0, 0 },
    { "sched2",	'R', 1, 0, 0 },
    { "bbro",	'B', 1, 0, 0 },
    { "jump2",	'J', 1, 0, 0 },
*************** rest_of_compilation (decl)
*** 3509,3525 ****
    close_dump_file (DFI_flow2, print_rtl_with_bb, insns);
    timevar_pop (TV_FLOW2);
  
-   if (optimize > 0)
-     {
-       timevar_push (TV_IFCVT2);
-       open_dump_file (DFI_ce2, decl);
- 
-       if_convert (1);
- 
-       close_dump_file (DFI_ce2, print_rtl_with_bb, insns);
-       timevar_pop (TV_IFCVT2);
-     }
- 
  #ifdef HAVE_peephole2
    if (optimize > 0 && flag_peephole2)
      {
--- 3509,3514 ----
*************** rest_of_compilation (decl)
*** 3544,3549 ****
--- 3533,3549 ----
        timevar_pop (TV_RENAME_REGISTERS);
      }
  
+   if (optimize > 0)
+     {
+       timevar_push (TV_IFCVT2);
+       open_dump_file (DFI_ce2, decl);
+ 
+       if_convert (1);
+ 
+       close_dump_file (DFI_ce2, print_rtl_with_bb, insns);
+       timevar_pop (TV_IFCVT2);
+     }
+ 
  #ifdef INSN_SCHEDULING
    if (optimize > 0 && flag_schedule_insns_after_reload)
      {
*************** main (argc, argv)
*** 4633,4638 ****
--- 4633,4639 ----
    if (optimize >= 3)
      {
        flag_inline_functions = 1;
+       flag_rename_registers = 1;
      }
  
    if (optimize < 2 || optimize_size)


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