patch for IA-64 compilation failure due to assembler errors

Jim Wilson wilson@cygnus.com
Mon Oct 23 16:43:00 GMT 2000


This fixes a problem where we accidentally could emit
	cmp4.gtu p6, p7 = 0, r32
cmp4.gtu is a pseudo-op that does not accept 0 in its immediate range.  It
accepts 2^32 instead.  This is easily fixed by emitting r0 instead of 0.

This problem showed up while compiling LPRng.  Due to a quirk of the optimizer,
the obviously redundant instruction could not be optimized away.  We shouldn't
be relying on the optimizer to get rid of invalid instructions though, so
it needs to be fixed independent of the optimizer problem.  I believe the
optimizer problem was fixed when we switched from CCmode to BImode, but I
haven't verified that yet.

2000-10-23  Jim Wilson  <wilson@cygnus.com>

	* ia64.c (ia64_print_operand, case 'r'): Correct comment.  Handle
	CONST_INT.
	* ia64.md (cmpsi_adjusted): Use %r3.
	(cmpdi_adjusted): Likewise.

Index: ia64.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/ia64/ia64.c,v
retrieving revision 1.54
diff -p -r1.54 ia64.c
*** ia64.c	2000/10/13 06:26:38	1.54
--- ia64.c	2000/10/23 23:28:14
*************** ia64_print_operand (file, x, code)
*** 3261,3271 ****
        break;
  
      case 'r':
!       /* If this operand is the constant zero, write it as zero.  */
        if (GET_CODE (x) == REG)
  	fputs (reg_names[REGNO (x)], file);
        else if (x == CONST0_RTX (GET_MODE (x)))
  	fputs ("r0", file);
        else
  	output_operand_lossage ("invalid %%r value");
        return;
--- 3261,3274 ----
        break;
  
      case 'r':
!       /* If this operand is the constant zero, write it as register zero.
! 	 Any register, zero, or CONST_INT value is OK here.  */
        if (GET_CODE (x) == REG)
  	fputs (reg_names[REGNO (x)], file);
        else if (x == CONST0_RTX (GET_MODE (x)))
  	fputs ("r0", file);
+       else if (GET_CODE (x) == CONST_INT)
+ 	output_addr_const (file, x);
        else
  	output_operand_lossage ("invalid %%r value");
        return;
Index: ia64.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/ia64/ia64.md,v
retrieving revision 1.51
diff -p -r1.51 ia64.md
*** ia64.md	2000/10/19 23:21:14	1.51
--- ia64.md	2000/10/23 23:28:15
***************
*** 4200,4212 ****
    "cmp4.%C1 %0, %I0 = %3, %2"
    [(set_attr "type" "A")])
  
  (define_insn "*cmpsi_adjusted"
    [(set (match_operand:BI 0 "register_operand" "=c")
  	(match_operator:BI 1 "adjusted_comparison_operator"
  	   [(match_operand:SI 2 "gr_register_operand" "r")
  	    (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
    ""
!   "cmp4.%C1 %0, %I0 = %3, %2"
    [(set_attr "type" "A")])
  
  (define_insn "*cmpdi_normal"
--- 4200,4215 ----
    "cmp4.%C1 %0, %I0 = %3, %2"
    [(set_attr "type" "A")])
  
+ ;; We use %r3 because it is possible for us to match a 0, and two of the
+ ;; unsigned comparisons don't accept immediate operands of zero.
+ 
  (define_insn "*cmpsi_adjusted"
    [(set (match_operand:BI 0 "register_operand" "=c")
  	(match_operator:BI 1 "adjusted_comparison_operator"
  	   [(match_operand:SI 2 "gr_register_operand" "r")
  	    (match_operand:SI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
    ""
!   "cmp4.%C1 %0, %I0 = %r3, %2"
    [(set_attr "type" "A")])
  
  (define_insn "*cmpdi_normal"
***************
*** 4218,4230 ****
    "cmp.%C1 %0, %I0 = %3, %r2"
    [(set_attr "type" "A")])
  
  (define_insn "*cmpdi_adjusted"
    [(set (match_operand:BI 0 "register_operand" "=c")
  	(match_operator:BI 1 "adjusted_comparison_operator"
  	   [(match_operand:DI 2 "gr_register_operand" "r")
  	    (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
    ""
!   "cmp.%C1 %0, %I0 = %3, %2"
    [(set_attr "type" "A")])
  
  (define_insn "*cmpsf_internal"
--- 4221,4236 ----
    "cmp.%C1 %0, %I0 = %3, %r2"
    [(set_attr "type" "A")])
  
+ ;; We use %r3 because it is possible for us to match a 0, and two of the
+ ;; unsigned comparisons don't accept immediate operands of zero.
+ 
  (define_insn "*cmpdi_adjusted"
    [(set (match_operand:BI 0 "register_operand" "=c")
  	(match_operator:BI 1 "adjusted_comparison_operator"
  	   [(match_operand:DI 2 "gr_register_operand" "r")
  	    (match_operand:DI 3 "gr_reg_or_8bit_adjusted_operand" "rL")]))]
    ""
!   "cmp.%C1 %0, %I0 = %r3, %2"
    [(set_attr "type" "A")])
  
  (define_insn "*cmpsf_internal"


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