c/838: sparc-solaris2.7 extra testsuite failures when RTL checking

[Graham Stott]

"Kaveh R. Ghazi" wrote:
> 
>  > From: Graham Stott <grahams@redhat.com>
>  >
>  > ChangeLog
>  >
>  >      * expr.c (store_constructor): Pass alias set 0 if the target is a REG.
>  >
> 
> Thanks for tackling this Graham.
> 
>  > > gcc.dg/ultrasp1.c:9: RTL check: expected code `reg', have `const_int'
>  > > gcc.dg/ultrasp1.c:9: RTL check: expected code `reg', have `const_int'
>  > > gcc.dg/ultrasp1.c:9: RTL check: expected code `reg', have `const_int'
>  >
>  > For what its worth (not a lot) I don't get these on x86-linux. I suspect
>  > they are occuring in one of the machine dependent files. Unfortunately
>  > I can't tell because the file/line context info is missing.
> 
> Sorry, here it is.  You were right about the machine specific file, I
> guess you'll need to use an RTL checking cross compiler to
> sparc-sun-solaris2.7 to recreate the bug.
> 
> Executing on host: /teal/caip5/ghazi/gcc-testing/build/gcc/xgcc -B/teal/caip5/ghazi/gcc-testing/build/gcc/ /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c   -mcpu=ultrasparc -S  -o ultrasp1.s    (timeout = 300)
> spawn /teal/caip5/ghazi/gcc-testing/build/gcc/xgcc -B/teal/caip5/ghazi/gcc-testing/build/gcc/ /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c -mcpu=ultrasparc -S -o ultrasp1.s
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c: In function `foo':
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c:9: RTL check: expected code `reg', have `const_int'
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c:9: Internal compiler error in print_operand, at config/sparc/sparc.c:5697
> confused by earlier errors, bailing out
> compiler exited with status 1
> output is:
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c: In function `foo':
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c:9: RTL check: expected code `reg', have `const_int'
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c:9: Internal compiler error in print_operand, at config/sparc/sparc.c:5697
> confused by earlier errors, bailing out
> 
> FAIL: gcc.dg/ultrasp1.c (test for excess errors)
> Excess errors:
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c:9: RTL check: expected code `reg', have `const_int'
> /teal/caip5/ghazi/gcc-testing/egcs-CVS20001120/gcc/testsuite/gcc.dg/ultrasp1.c:9: Internal compiler error in print_operand, at config/sparc/sparc.c:5697
> confused by earlier errors, bailing out

Here's the relevant code from sparc.c

    case 'L':
      /* Print out the low order register name of a register pair.  */
      if (WORDS_BIG_ENDIAN)
        fputs (reg_names[REGNO (x)+1], file);
      else
        fputs (reg_names[REGNO (x)], file);
      return;

It looks to me to be a bug in the sparc.md file here's the offending pattern.

;; V8plus wide multiply.
;; XXX
(define_insn "muldi3_v8plus"
  [(set (match_operand:DI 0 "register_operand" "=r,h")
        (mult:DI (match_operand:DI 1 "arith_double_operand" "%r,0")
                 (match_operand:DI 2 "arith_double_operand" "rHI,rHI")))
   (clobber (match_scratch:SI 3 "=&h,X"))
   (clobber (match_scratch:SI 4 "=&h,X"))]
  "TARGET_V8PLUS"
  "*
{
  if (sparc_check_64 (operands[1], insn) <= 0)
    output_asm_insn (\"srl\\t%L1, 0, %L1\", operands);
  if (which_alternative == 1)
    output_asm_insn (\"sllx\\t%H1, 32, %H1\", operands);
  if (sparc_check_64 (operands[2], insn) <= 0)
    output_asm_insn (\"srl\\t%L2, 0, %L2\", operands);
  if (which_alternative == 1)
    return \"or\\t%L1, %H1, %H1\\n\\tsllx\\t%H2, 32, %L1\\n\\tor\\t%L2, %L1, %L1\\n\\tmulx\\t%H1, %L1, %L0\;srlx\\t%L0, 32, %H0\";
  else
    return \"sllx\\t%H1, 32, %3\\n\\tsllx\\t%H2, 32, %4\\n\\tor\\t%L1, %3, %3\\n\\tor\\t%L2, %4, %4\\n\\tmulx\\t%3, %4, %3\\n\\tsrlx\\t%3, 32, %H0\\n\\tmov\\t%3, %L0\";
}"
  [(set_attr "length" "9,8")])

The relevant values are

	operand 0 (reg:DI 24 %i0)
	operand 1 (reg:DI 24 %i0)
	operand 2 (const_int -1 [0xffffffff])

and
	which_alternative is 0

The problem occurs in this because operand 2 is not a register.

	output_asm_insn (\"srl\\t%L2, 0, %L2\", operands);

My knowledge of sparc code is nil so I've got no idea how to fix this.

Richard any idea?

Graham