multi-insn increment patches part 3/3: avoiding double registering ofbiv increments

[Joern Rennecke]

On x86, when compiling g77.f-torture/compile/20000518.f,  -O3 -fssa,
ssa leaves a no-op move - insn 89:

(insn 75 73 76 (parallel[ 
            (set (reg:SI 48)
                (plus:SI (reg:SI 48)
                    (const_int -1 [0xffffffff])))
            (clobber (reg:CC 17 flags))
        ] ) 111 {*addsi_1} (nil)
    (nil))

(insn 76 75 78 (parallel[ 
            (set (reg:SI 49)
                (mult:SI (reg:SI 48)
                    (reg:SI 35)))
            (clobber (reg:CC 17 flags))
        ] ) 132 {*mulsi3_1} (nil)
    (nil))

(insn 78 76 80 (parallel[ 
            (set (reg:SI 50)
                (plus:SI (reg:SI 47)
                    (reg:SI 49)))
            (clobber (reg:CC 17 flags))
        ] ) 111 {*addsi_1} (nil)
    (nil))

(insn 80 78 82 (parallel[ 
            (set (reg:SI 51)
                (plus:SI (reg:SI 50)
                    (const_int -4 [0xfffffffc])))
            (clobber (reg:CC 17 flags))
        ] ) 111 {*addsi_1} (nil)
    (nil))

(insn 82 80 84 (set (mem/s:SF (plus:SI (reg/v/u:SI 27)
                (reg:SI 51)) 0)
        (const_double:SF (cc0) 0 [0x0] 0 [0x0] 0 [0x0])) 55 {*movsf_1} (nil)
    (nil))

(note 84 82 89 NOTE_INSN_LOOP_CONT 0)

(insn 89 84 120 (set (reg:SI 48)
        (reg:SI 48)) 32 {*movsi_1} (nil)
    (nil))

(note 120 89 42 NOTE_INSN_LOOP_VTOP 0)

currently, basic_induction_variable will consider insn 89 to be a biv
increment, using the increment of insn 75.  However, insn 75 is a biv
increment in its own right.

Thu May 25 01:47:36 2000  J"orn Rennecke <amylaar@cygnus.co.uk>

	* loop.c (basic_induction_var): Avoid double recording of an increment.

*** loop.c-20000524	Wed May 24 21:52:55 2000
--- loop.c	Thu May 25 01:44:19 2000
*************** basic_induction_var (loop, x, mode, dest
*** 5995,6000 ****
--- 5995,6005 ----
        /* If this register is assigned in a previous insn, look at its
  	 source, but don't go outside the loop or past a label.  */
  
+       /* If this sets a register to itself, we would repeat any previous
+ 	 biv increment if we applied this strategy blindly.  */
+       if (rtx_equal_p (dest_reg, x))
+ 	return 0;
+ 
        insn = p;
        while (1)
  	{
*************** basic_induction_var (loop, x, mode, dest
*** 6066,6072 ****
        if (insn)
  	set = single_set (insn);
  
!       if (set && SET_DEST (set) == XEXP (x, 0)
  	  && GET_CODE (XEXP (x, 1)) == CONST_INT
  	  && INTVAL (XEXP (x, 1)) >= 0
  	  && GET_CODE (SET_SRC (set)) == ASHIFT
--- 6071,6078 ----
        if (insn)
  	set = single_set (insn);
  
!       if (! rtx_equal_p (dest_reg, XEXP (x, 0))
! 	  && set && SET_DEST (set) == XEXP (x, 0)
  	  && GET_CODE (XEXP (x, 1)) == CONST_INT
  	  && INTVAL (XEXP (x, 1)) >= 0
  	  && GET_CODE (SET_SRC (set)) == ASHIFT