Patch for alpha -mno-fp-regs

Michael Meissner meissner@redhat.com
Tue Mar 21 10:55:00 GMT 2000


One of Cygnus's customers reported that the mppe code added to the
Linux kernel generated a fatal insn due to not being able to allocate
a floating point.  While I would argue that the code is wrong to try
and use floating point in the kernel, the compiler should still be
able to handle the code without aborting.  In generating the patch, I
discovered that the recent TF support also didn't check for whether
you could use the FP registers, so I added appropriate tests for this
case as well.  I installed these patches under the obvious rule after
doing a bootstrap.

2000-03-21  Michael Meissner  <meissner@redhat.com>

	* config/alpha/alpha.md (floating point insns): Add TARGET_FP to
	all floating point insns that just tested the macro
	TARGET_HAS_XFLOATING_LIBS.
	(movsf/movdf recognizers): Add separate insns if -mno-fp-regs is
	used to only use the gprs.

*** gcc/config/alpha/alpha.md.~1~	Tue Mar 21 00:34:14 2000
--- gcc/config/alpha/alpha.md	Tue Mar 21 12:23:19 2000
***************
*** 2093,2099 ****
  (define_expand "fix_trunctfdi2"
    [(use (match_operand:DI 0 "register_operand" ""))
     (use (match_operand:TF 1 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
  
  (define_insn ""
--- 2093,2099 ----
  (define_expand "fix_trunctfdi2"
    [(use (match_operand:DI 0 "register_operand" ""))
     (use (match_operand:TF 1 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
  
  (define_insn ""
***************
*** 2131,2155 ****
  (define_expand "floatditf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:DI 1 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
  
  (define_expand "floatunsdisf2"
    [(use (match_operand:SF 0 "register_operand" ""))
     (use (match_operand:DI 1 "register_operand" ""))]
!   ""
    "alpha_emit_floatuns (operands); DONE;")
  
  (define_expand "floatunsdidf2"
    [(use (match_operand:DF 0 "register_operand" ""))
     (use (match_operand:DI 1 "register_operand" ""))]
!   ""
    "alpha_emit_floatuns (operands); DONE;")
  
  (define_expand "floatunsditf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:DI 1 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
  
  (define_expand "extendsfdf2"
--- 2131,2155 ----
  (define_expand "floatditf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:DI 1 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
  
  (define_expand "floatunsdisf2"
    [(use (match_operand:SF 0 "register_operand" ""))
     (use (match_operand:DI 1 "register_operand" ""))]
!   "TARGET_FP"
    "alpha_emit_floatuns (operands); DONE;")
  
  (define_expand "floatunsdidf2"
    [(use (match_operand:DF 0 "register_operand" ""))
     (use (match_operand:DI 1 "register_operand" ""))]
!   "TARGET_FP"
    "alpha_emit_floatuns (operands); DONE;")
  
  (define_expand "floatunsditf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:DI 1 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
  
  (define_expand "extendsfdf2"
***************
*** 2183,2189 ****
  (define_expand "extendsftf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:SF 1 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "
  {
    rtx tmp = gen_reg_rtx (DFmode);
--- 2183,2189 ----
  (define_expand "extendsftf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:SF 1 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "
  {
    rtx tmp = gen_reg_rtx (DFmode);
***************
*** 2195,2201 ****
  (define_expand "extenddftf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:DF 1 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
  
  (define_insn ""
--- 2195,2201 ----
  (define_expand "extenddftf2"
    [(use (match_operand:TF 0 "register_operand" ""))
     (use (match_operand:DF 1 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
  
  (define_insn ""
***************
*** 2217,2229 ****
  (define_expand "trunctfdf2"
    [(use (match_operand:DF 0 "register_operand" ""))
     (use (match_operand:TF 1 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
  
  (define_expand "trunctfsf2"
    [(use (match_operand:SF 0 "register_operand" ""))
     (use (match_operand:TF 1 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "
  {
    rtx tmpf, sticky, arg, lo, hi;
--- 2217,2229 ----
  (define_expand "trunctfdf2"
    [(use (match_operand:DF 0 "register_operand" ""))
     (use (match_operand:TF 1 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
  
  (define_expand "trunctfsf2"
    [(use (match_operand:SF 0 "register_operand" ""))
     (use (match_operand:TF 1 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "
  {
    rtx tmpf, sticky, arg, lo, hi;
***************
*** 2317,2323 ****
    [(use (match_operand 0 "register_operand" ""))
     (use (match_operand 1 "general_operand" ""))
     (use (match_operand 2 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_arith (DIV, operands); DONE;")
  
  (define_insn ""
--- 2317,2323 ----
    [(use (match_operand 0 "register_operand" ""))
     (use (match_operand 1 "general_operand" ""))
     (use (match_operand 2 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_arith (DIV, operands); DONE;")
  
  (define_insn ""
***************
*** 2381,2387 ****
    [(use (match_operand 0 "register_operand" ""))
     (use (match_operand 1 "general_operand" ""))
     (use (match_operand 2 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_arith (MULT, operands); DONE;")
  
  (define_insn ""
--- 2381,2387 ----
    [(use (match_operand 0 "register_operand" ""))
     (use (match_operand 1 "general_operand" ""))
     (use (match_operand 2 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_arith (MULT, operands); DONE;")
  
  (define_insn ""
***************
*** 2455,2461 ****
    [(use (match_operand 0 "register_operand" ""))
     (use (match_operand 1 "general_operand" ""))
     (use (match_operand 2 "general_operand" ""))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
  
  (define_insn ""
--- 2455,2461 ----
    [(use (match_operand 0 "register_operand" ""))
     (use (match_operand 1 "general_operand" ""))
     (use (match_operand 2 "general_operand" ""))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
  
  (define_insn ""
***************
*** 3172,3178 ****
  (define_expand "cmptf"
    [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
  		       (match_operand:TF 1 "general_operand" "")))]
!   "TARGET_HAS_XFLOATING_LIBS"
    "
  {
    alpha_compare.op0 = operands[0];
--- 3172,3178 ----
  (define_expand "cmptf"
    [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
  		       (match_operand:TF 1 "general_operand" "")))]
!   "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
    "
  {
    alpha_compare.op0 = operands[0];
***************
*** 4209,4215 ****
  (define_insn ""
    [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
  	(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
!   "! TARGET_FIX
     && (register_operand (operands[0], SFmode)
         || reg_or_fp0_operand (operands[1], SFmode))"
    "@
--- 4209,4215 ----
  (define_insn ""
    [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
  	(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
!   "TARGET_FPREGS && ! TARGET_FIX
     && (register_operand (operands[0], SFmode)
         || reg_or_fp0_operand (operands[1], SFmode))"
    "@
***************
*** 4224,4230 ****
  (define_insn ""
    [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
  	(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
!   "TARGET_FIX
     && (register_operand (operands[0], SFmode)
         || reg_or_fp0_operand (operands[1], SFmode))"
    "@
--- 4224,4230 ----
  (define_insn ""
    [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
  	(match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
!   "TARGET_FPREGS && TARGET_FIX
     && (register_operand (operands[0], SFmode)
         || reg_or_fp0_operand (operands[1], SFmode))"
    "@
***************
*** 4239,4247 ****
    [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
  
  (define_insn ""
    [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
  	(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
!   "! TARGET_FIX
     && (register_operand (operands[0], DFmode)
         || reg_or_fp0_operand (operands[1], DFmode))"
    "@
--- 4239,4259 ----
    [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
  
  (define_insn ""
+   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
+ 	(match_operand:SF 1 "input_operand" "rG,m,r"))]
+   "! TARGET_FPREGS
+    && (register_operand (operands[0], SFmode)
+        || reg_or_fp0_operand (operands[1], SFmode))"
+   "@
+    mov %r1,%0
+    ldl %0,%1
+    stl %r1,%0"
+   [(set_attr "type" "ilog,ild,ist")])
+ 
+ (define_insn ""
    [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
  	(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
!   "TARGET_FPREGS && ! TARGET_FIX
     && (register_operand (operands[0], DFmode)
         || reg_or_fp0_operand (operands[1], DFmode))"
    "@
***************
*** 4256,4262 ****
  (define_insn ""
    [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
  	(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
!   "TARGET_FIX
     && (register_operand (operands[0], DFmode)
         || reg_or_fp0_operand (operands[1], DFmode))"
    "@
--- 4268,4274 ----
  (define_insn ""
    [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
  	(match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
!   "TARGET_FPREGS && TARGET_FIX
     && (register_operand (operands[0], DFmode)
         || reg_or_fp0_operand (operands[1], DFmode))"
    "@
***************
*** 4269,4274 ****
--- 4281,4298 ----
     itoft %1,%0
     ftoit %1,%0"
    [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
+ 
+ (define_insn ""
+   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
+ 	(match_operand:DF 1 "input_operand" "rG,m,r"))]
+   "! TARGET_FPREGS
+    && (register_operand (operands[0], DFmode)
+        || reg_or_fp0_operand (operands[1], DFmode))"
+   "@
+    mov %r1,%0
+    ldq %0,%1
+    stq %r1,%0"
+   [(set_attr "type" "ilog,ild,ist")])
  
  ;; Subregs suck for register allocation.  Pretend we can move TFmode
  ;; data between general registers until after reload.

-- 
Michael Meissner, Cygnus Solutions, a Red Hat company.
PMB 198, 174 Littleton Road #3, Westford, Massachusetts 01886, USA
Work:	  meissner@redhat.com		phone: +1 978-486-9304
Non-work: meissner@spectacle-pond.org	fax:   +1 978-692-4482


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