ppc prolog scheduling/fpmem register removal
Geoff Keating
geoffk@cygnus.com
Wed Jan 19 15:33:00 GMT 2000
This eliminates the bizzare fpmem hard register.
The problem with doing this in a scheduled prolog is that
accesses to the fpmem register really use the stack and/or
frame pointer, and don't say so.
Of course, the old code was pretty broken anyway.
A happy side-effect is that this fixes many warnings from genrecog for
rs6000.md. And it halves the number of 'unspec' codes used.
I'll nuke the fpmem-handling code (in rs6000.c, rs6000.h, dozens of
places) later. It shouldn't be used since the fpmem register will
never be live.
--
- Geoffrey Keating <geoffk@cygnus.com>
===File ~/patches/cygnus/rs6000-psched-3-fpmem-2.patch======
Index: ChangeLog
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/Attic/ChangeLog,v
retrieving revision 1.1.2.16
diff -p -u -c -F^( -r1.1.2.16 ChangeLog
*** ChangeLog 2000/01/19 23:08:37 1.1.2.16
--- ChangeLog 2000/01/19 23:15:30
***************
*** 1,3 ****
--- 1,29 ----
+ 2000-01-19 Geoff Keating <geoffk@cygnus.com>
+
+ * rs6000.md (floatsidf2): Don't use the fpmem "register", just
+ allocate a stack temporary.
+ (floatsidf2_internal): Likewise.
+ (floatsidf2_internal+1): Likewise. Don't do bizzare hacks
+ with unspec.
+ (floatunssidf2): Don't use the fpmem "register", just
+ allocate a stack temporary.
+ (floatunssidf2_internal): Likewise.
+ (floatunssidf2_internal+1): Likewise. Don't do bizzare hacks
+ with unspec.
+ (floatsidf2_loadaddr): Delete.
+ (floatsidf2_store1): Delete.
+ (floatsidf2_store2): Delete.
+ (floatsidf2_load): Delete.
+ (fix_truncdfsi2): Don't use the fpmem "register", just
+ allocate a stack temporary.
+ (fix_truncdfsi2_internal_si): Delete.
+ (fix_truncdfsi2_internal_di): Delete.
+ (fix_truncdfsi2_internal): New insn.
+ (fix_truncdfsi2_internal+1): Don't use the fpmem "register".
+ (fix_truncdfsi2_store): Delete.
+ (fix_truncdfsi2_load): Delete.
+ (fctiwz): Produce gen_fctiwz.
+
2000-01-19 Geoffrey Keating <geoffk@cygnus.com>
* eabi.h (INVOKE__main): Define.
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.79.2.5
diff -p -u -c -F^( -r1.79.2.5 rs6000.md
*** rs6000.md 2000/01/13 01:43:10 1.79.2.5
--- rs6000.md 2000/01/19 23:15:31
***************
*** 29,40 ****
;; 7 clobber SP for NT
;; 7 address of the GOT under SVR4 -fpic
;; 8 movsi_got
- ;; 11 floatsidf2_loadaddr
- ;; 12 floatsidf2_store1
- ;; 13 floatsidf2_store2
- ;; 14 floatsidf2_load
- ;; 15 fix_truncdfsi2_store
- ;; 16 fix_truncdfsi2_load
;; 20 movesi_to_cr
;; Define an insn type attribute. This is used in function unit delay
--- 29,34 ----
*************** (define_insn "fselsfdf4"
*** 4189,4194 ****
--- 4183,4193 ----
;; Conversions to and from floating-point.
+ ; For each of these conversions, there is a define_expand, a define_insn
+ ; with a '#' template, and a define_split (with C code). The idea is
+ ; to allow constant folding with the template of the define_insn,
+ ; then to have the insns split later (between sched1 and final).
+
(define_expand "floatsidf2"
[(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
*************** (define_expand "floatsidf2"
*** 4196,4209 ****
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))
! (clobber (reg:DF 76))])]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"
{
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
! operands[4] = gen_reg_rtx (SImode);
! operands[5] = gen_reg_rtx (Pmode);
}")
(define_insn "*floatsidf2_internal"
--- 4195,4209 ----
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))
! (clobber (match_dup 6))])]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"
{
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
! operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
! operands[5] = gen_reg_rtx (DFmode);
! operands[6] = gen_reg_rtx (SImode);
}")
(define_insn "*floatsidf2_internal"
*************** (define_insn "*floatsidf2_internal"
*** 4211,4219 ****
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r"))
(use (match_operand:DF 3 "gpc_reg_operand" "f"))
! (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
! (clobber (match_operand:SI 5 "gpc_reg_operand" "=b"))
! (clobber (reg:DF 76))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"#"
[(set_attr "length" "24")])
--- 4211,4219 ----
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r"))
(use (match_operand:DF 3 "gpc_reg_operand" "f"))
! (clobber (match_operand:DF 4 "memory_operand" "=o"))
! (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))
! (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"#"
[(set_attr "length" "24")])
*************** (define_split
*** 4223,4254 ****
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
! (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
! (clobber (match_operand 5 "gpc_reg_operand" ""))
! (clobber (reg:DF 76))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
! [(set (match_dup 4)
! (xor:SI (match_dup 1)
! (match_dup 6)))
! (set (match_dup 5)
! (unspec [(const_int 0)] 11))
! (set (match_dup 7)
! (unspec [(match_dup 4)
! (match_dup 5)] 12)) ;; low word
! (set (match_dup 7)
! (unspec [(match_dup 2)
! (match_dup 5)
! (match_dup 7)] 13)) ;; high word
! (set (match_dup 0)
! (unspec [(match_dup 7)
! (match_dup 5)] 14))
! (set (match_dup 0)
! (minus:DF (match_dup 0)
! (match_dup 3)))]
"
{
! operands[6] = GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff);
! operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM);
}")
(define_expand "floatunssidf2"
--- 4223,4259 ----
(float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
! (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
! (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
! (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
! (use (match_operand:SI 2 "gpc_reg_operand" ""))
! (use (match_operand:DF 3 "gpc_reg_operand" ""))
! (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
! (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
! (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
"
{
! rtx lowword, highword;
! if (GET_CODE (operands[4]) != MEM)
! abort();
! highword = XEXP (operands[4], 0);
! lowword = plus_constant (highword, 4);
! if (! WORDS_BIG_ENDIAN)
! {
! rtx tmp;
! tmp = highword; highword = lowword; lowword = tmp;
! }
!
! emit_insn (gen_xorsi3 (operands[6], operands[1],
! GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
! emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
! emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
! emit_move_insn (operands[5], operands[4]);
! emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
! DONE;
}")
(define_expand "floatunssidf2"
*************** (define_expand "floatunssidf2"
*** 4257,4269 ****
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 4))
! (clobber (reg:DF 76))])]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"
{
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
! operands[4] = gen_reg_rtx (Pmode);
}")
(define_insn "*floatunssidf2_internal"
--- 4262,4275 ----
(use (match_dup 2))
(use (match_dup 3))
(clobber (match_dup 4))
! (clobber (match_dup 5))])]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"
{
operands[2] = force_reg (SImode, GEN_INT (0x43300000));
operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
! operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
! operands[5] = gen_reg_rtx (DFmode);
}")
(define_insn "*floatunssidf2_internal"
*************** (define_insn "*floatunssidf2_internal"
*** 4271,4278 ****
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r"))
(use (match_operand:DF 3 "gpc_reg_operand" "f"))
! (clobber (match_operand:SI 4 "gpc_reg_operand" "=b"))
! (clobber (reg:DF 76))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"#"
[(set_attr "length" "20")])
--- 4277,4284 ----
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
(use (match_operand:SI 2 "gpc_reg_operand" "r"))
(use (match_operand:DF 3 "gpc_reg_operand" "f"))
! (clobber (match_operand:DF 4 "memory_operand" "=o"))
! (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
"#"
[(set_attr "length" "20")])
*************** (define_split
*** 4282,4415 ****
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
! (clobber (match_operand 4 "gpc_reg_operand" ""))
! (clobber (reg:DF 76))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
! [(set (match_dup 4)
! (unspec [(const_int 0)] 11))
! (set (match_dup 5)
! (unspec [(match_dup 1)
! (match_dup 4)] 12)) ;; low word
! (set (match_dup 5)
! (unspec [(match_dup 2)
! (match_dup 4)
! (match_dup 5)] 13)) ;; high word
! (set (match_dup 0)
! (unspec [(match_dup 5)
! (match_dup 4)] 14))
! (set (match_dup 0)
! (minus:DF (match_dup 0)
! (match_dup 3)))]
! "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);")
!
! ;; Load up scratch register with base address + offset if needed
! (define_insn "*floatsidf2_loadaddr"
! [(set (match_operand 0 "gpc_reg_operand" "=b")
! (unspec [(const_int 0)] 11))]
! "TARGET_HARD_FLOAT"
! "*
! {
! if (rs6000_fpmem_offset > 32760)
! {
! rtx xop[3];
!
! xop[0] = operands[0];
! xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
! xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15));
! output_asm_insn (\"{cau|addis} %0,%1,%2\", xop);
! }
!
! return \"\";
! }"
! [(set_attr "length" "4")])
!
! (define_insn "*floatsidf2_store1"
! [(set (reg:DF 76)
! (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
! (match_operand:SI 1 "gpc_reg_operand" "b")] 12))]
! "TARGET_HARD_FLOAT"
! "*
! {
! rtx indx;
!
! if (rs6000_fpmem_offset > 32760)
! indx = operands[1];
! else if (frame_pointer_needed)
! indx = frame_pointer_rtx;
! else
! indx = stack_pointer_rtx;
!
! operands[2]
! = gen_rtx_MEM (SImode,
! plus_constant (indx,
! (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
! - 0x8000)
! + ((WORDS_BIG_ENDIAN != 0) * 4)));
!
! return \"{st|stw} %0,%2\";
! }"
! [(set_attr "type" "store")])
!
! (define_insn "*floatsidf2_store2"
! [(set (reg:DF 76)
! (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
! (match_operand:SI 1 "gpc_reg_operand" "b")
! (reg:DF 76)] 13))]
! "TARGET_HARD_FLOAT"
! "*
! {
! rtx indx;
!
! if (rs6000_fpmem_offset > 32760)
! indx = operands[1];
! else if (frame_pointer_needed)
! indx = frame_pointer_rtx;
! else
! indx = stack_pointer_rtx;
!
! operands[2]
! = gen_rtx_MEM (SImode,
! plus_constant (indx,
! (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
! - 0x8000)
! + ((WORDS_BIG_ENDIAN == 0) * 4)));
!
! return \"{st|stw} %0,%2\";
! }"
! [(set_attr "type" "store")])
!
! (define_insn "*floatsidf2_load"
! [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
! (unspec [(reg:DF 76)
! (match_operand:SI 1 "gpc_reg_operand" "b")] 14))]
! "TARGET_HARD_FLOAT"
! "*
{
! rtx indx;
! HOST_WIDE_INT offset = rs6000_fpmem_offset;
!
! if (rs6000_fpmem_offset > 32760)
{
! indx = operands[1];
! offset = (((offset & 0xffff) ^ 0x8000) - 0x8000);
}
- else if (frame_pointer_needed)
- indx = frame_pointer_rtx;
- else
- indx = stack_pointer_rtx;
-
- operands[2] = gen_rtx_MEM (SImode, plus_constant (indx, offset));
! return \"lfd %0,%2\";
! }"
! [(set_attr "type" "fpload")])
(define_expand "fix_truncdfsi2"
[(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2))
! (clobber (match_dup 3))
! (clobber (match_dup 4))])]
"TARGET_HARD_FLOAT"
"
{
--- 4288,4327 ----
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
(use (match_operand:SI 2 "gpc_reg_operand" ""))
(use (match_operand:DF 3 "gpc_reg_operand" ""))
! (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
! (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
! (use (match_operand:SI 2 "gpc_reg_operand" ""))
! (use (match_operand:DF 3 "gpc_reg_operand" ""))
! (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
! (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
! "
{
! rtx lowword, highword;
! if (GET_CODE (operands[4]) != MEM)
! abort();
! highword = XEXP (operands[4], 0);
! lowword = plus_constant (highword, 4);
! if (! WORDS_BIG_ENDIAN)
{
! rtx tmp;
! tmp = highword; highword = lowword; lowword = tmp;
}
! emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
! emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
! emit_move_insn (operands[5], operands[4]);
! emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
! DONE;
! }")
(define_expand "fix_truncdfsi2"
[(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2))
! (clobber (match_dup 3))])]
"TARGET_HARD_FLOAT"
"
{
*************** (define_expand "fix_truncdfsi2"
*** 4421,4521 ****
}
operands[2] = gen_reg_rtx (DImode);
! operands[3] = gen_reg_rtx (Pmode);
! operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);
}")
! (define_insn "*fix_truncdfsi2_internal_si"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
! (clobber (match_operand:SI 3 "gpc_reg_operand" "=b"))
! (clobber (reg:DI 76))]
! "TARGET_HARD_FLOAT && ! TARGET_POWERPC64"
! "#"
! [(set_attr "length" "12")])
!
! (define_insn "*fix_truncdfsi2_internal_di"
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
! (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
! (clobber (match_operand:DI 3 "gpc_reg_operand" "=b"))
! (clobber (reg:DI 76))]
! "TARGET_HARD_FLOAT && TARGET_POWERPC64"
"#"
! [(set_attr "length" "12")])
(define_split
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" ""))
! (clobber (match_operand 3 "gpc_reg_operand" ""))
! (clobber (reg:DI 76))]
"TARGET_HARD_FLOAT"
! [(clobber (match_dup 2))
! (set (subreg:SI (match_dup 2) 0)
! (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
! (set (match_dup 3)
! (unspec [(const_int 0)] 11))
! (set (match_dup 4)
! (unspec [(match_dup 2)
! (match_dup 3)] 15))
! (set (match_operand:SI 0 "gpc_reg_operand" "")
! (unspec [(match_dup 4)
! (match_dup 3)] 16))]
! "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);")
!
! (define_insn "*fix_truncdfsi2_store"
! [(set (reg:DI 76)
! (unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
! (match_operand 1 "gpc_reg_operand" "b")] 15))]
! "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
! "*
! {
! rtx indx;
!
! if (rs6000_fpmem_offset > 32760)
! indx = operands[1];
! else if (frame_pointer_needed)
! indx = frame_pointer_rtx;
! else
! indx = stack_pointer_rtx;
!
! operands[2] = gen_rtx_MEM (DFmode,
! plus_constant (indx,
! (((rs6000_fpmem_offset & 0xffff)
! ^ 0x8000) - 0x8000)));
!
! return \"stfd %0,%2\";
! }"
! [(set_attr "type" "fpstore")])
!
! (define_insn "*fix_truncdfsi2_load"
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! (unspec [(reg:DI 76)
! (match_operand 1 "gpc_reg_operand" "b")] 16))]
! "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
! "*
{
! rtx indx;
!
! if (rs6000_fpmem_offset > 32760)
! indx = operands[1];
! else if (frame_pointer_needed)
! indx = frame_pointer_rtx;
! else
! indx = stack_pointer_rtx;
!
! operands[2]
! = gen_rtx_MEM (DFmode,
! plus_constant (indx,
! (((rs6000_fpmem_offset & 0xffff) ^ 0x8000)
! - 0x8000)
! + ((WORDS_BIG_ENDIAN) ? 4 : 0)));
!
! return \"{l|lwz} %0,%2\";
! }"
! [(set_attr "type" "load")])
(define_expand "fixuns_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
--- 4333,4374 ----
}
operands[2] = gen_reg_rtx (DImode);
! operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
}")
! (define_insn "*fix_truncdfsi2_internal"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
! (clobber (match_operand:DI 3 "memory_operand" "=o"))]
! "TARGET_HARD_FLOAT"
"#"
! [(set_attr "length" "16")])
(define_split
[(set (match_operand:SI 0 "gpc_reg_operand" "")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
(clobber (match_operand:DI 2 "gpc_reg_operand" ""))
! (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
"TARGET_HARD_FLOAT"
! [(set (match_operand:SI 0 "gpc_reg_operand" "")
! (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
! (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
! (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
! "
{
! rtx lowword;
! if (GET_CODE (operands[3]) != MEM)
! abort();
! lowword = XEXP (operands[3], 0);
! if (WORDS_BIG_ENDIAN)
! lowword = plus_constant (lowword, 4);
!
! emit_insn (gen_fctiwz (operands[2], operands[1]));
! emit_move_insn (operands[3], operands[2]);
! emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
! DONE;
! }")
(define_expand "fixuns_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "")
*************** (define_expand "trunc_call_rtl"
*** 4562,4568 ****
rs6000_trunc_used = 1;
}")
! (define_insn "*fctiwz"
[(set (subreg:SI (match_operand:DI 0 "gpc_reg_operand" "=f") 0)
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
--- 4415,4421 ----
rs6000_trunc_used = 1;
}")
! (define_insn "fctiwz"
[(set (subreg:SI (match_operand:DI 0 "gpc_reg_operand" "=f") 0)
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))]
"(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
============================================================
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