[PATCH] Updated -mlive-g0 patch for SPARC

Jakub Jelinek jakub@redhat.com
Tue Feb 22 08:02:00 GMT 2000


Hi!

My -mlive-g0 patch no longer applies cleanly, so I'm resending it. Ok to
commit?

This patch does two things (if that causes problems, will split it):
a) fixes sparc64 -mno-fpu compilation, where it could abort because
   (set (reg:DF) (reg:DF)) was allowed to go into the epilogue delay,
   while there was no such pattern to handle it
b) Almost removes TARGET_LIVEG0 and TARGET_BROKEN_SAVERESTORE:
   the only target which has -mlive-g0 and -mbroken-saverestore is splet,
   but splet.h in SUBTARGET_OVERRIDE_OPTIONS warns about these switches
   and disables them, so on no sparc port are they actually used, and they
   clutter especially the .md file a lot. Some patterns can be deleted
   because of this, plus in the future (e.g. when myself or David rewrite
   the movdf patterns) we don't have to create separate noliveg0 patterns.

2000-02-22  Jakub Jelinek  <jakub@redhat.com>

	* config/sparc/sparc.md: Remove all traces of TARGET_LIVE_G0.
	(movsi_zero_liveg0): Remove.
	(movsf_insn_novis_liveg0): Remove.
	(negsi2): Remove.
	(negsi2_not_liveg0): Rename to negsi2.
	(one_cmplsi2): Remove.
	(one_cmplsi2_not_liveg0): Rename to one_cmplsi2.
	(one_cmplsi2_liveg0): Remove.
	* config/sparc/sparc.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Default to 0, update comments.
	(CONDITIONAL_REGISTER_USAGE): Remove TARGET_LIVE_G0 if.
	(PREDICATE_CODES): Remove zero_operand.
	* config/sparc/sparc.c: Remove all traces of TARGET_LIVE_G0 and
	TARGET_BROKEN_SAVERESTORE.
	(zero_operand): Remove.
	* config/sparc/splet.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Define.
	* config/sparc/linux-aout.h (TARGET_LIVE_G0,
	TARGET_BROKEN_SAVERESTORE): Remove.
	* config/sparc/linux.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Remove.
	* config/sparc/linux64.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Remove.
	* config/sparc/sol2.h (TARGET_LIVE_G0, TARGET_BROKEN_SAVERESTORE):
	Remove.

	* config/sparc/sparc.md (return_df_no_fpu): New pattern.

--- gcc/config/sparc/sparc.md.jj	Mon Feb 21 08:18:26 2000
+++ gcc/config/sparc/sparc.md	Tue Feb 22 16:33:05 2000
@@ -57,9 +57,6 @@
 ;; is a bit of a misnomer as it covers all 64 fp regs.  The corresponding
 ;; constraint letter is 'e'.  To avoid any confusion, 'e' is used instead of
 ;; 'f' for all DF/TFmode values, including those that are specific to the v8.
-;;
-;; -mlive-g0 is *not* supported for TARGET_ARCH64, so we don't bother to
-;; test TARGET_LIVE_G0 if we have TARGET_ARCH64.
 
 ;; Attribute for cpu type.
 ;; These must match the values for enum processor_type in sparc.h.
@@ -82,12 +79,6 @@
   (cond [(symbol_ref "TARGET_ARCH64") (const_string "arch64bit")]
 	(const_string "arch32bit"))))
 
-;; Whether -mlive-g0 is in effect.
-(define_attr "live_g0" "no,yes"
- (const
-  (cond [(symbol_ref "TARGET_LIVE_G0") (const_string "yes")]
-	(const_string "no"))))
-
 ;; Insn type.  Used to default other attribute values.
 
 ;; type "unary" insns have one input operand (1) and one output operand (0)
@@ -748,7 +739,7 @@
    (parallel [(set (match_operand:SI 0 "register_operand" "")
 		   (eq:SI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
-  "! TARGET_LIVE_G0"
+  ""
   "{ operands[3] = gen_reg_rtx (SImode); }")
 
 (define_expand "seqdi_special"
@@ -767,7 +758,7 @@
    (parallel [(set (match_operand:SI 0 "register_operand" "")
 		   (ne:SI (match_dup 3) (const_int 0)))
 	      (clobber (reg:CC 100))])]
-  "! TARGET_LIVE_G0"
+  ""
   "{ operands[3] = gen_reg_rtx (SImode); }")
 
 (define_expand "snedi_special"
@@ -822,7 +813,7 @@
 (define_expand "seq"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(eq:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == SImode)
@@ -875,7 +866,7 @@
 (define_expand "sne"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ne:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == SImode)
@@ -926,7 +917,7 @@
 (define_expand "sgt"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(gt:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
@@ -947,7 +938,7 @@
 (define_expand "slt"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(lt:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
@@ -968,7 +959,7 @@
 (define_expand "sge"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ge:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
@@ -989,7 +980,7 @@
 (define_expand "sle"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(le:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (GET_MODE (sparc_compare_op0) == TFmode && ! TARGET_HARD_QUAD)
@@ -1010,7 +1001,7 @@
 (define_expand "sgtu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(gtu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (! TARGET_V9)
@@ -1045,7 +1036,7 @@
 (define_expand "sltu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(ltu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (TARGET_V9)
@@ -1059,7 +1050,7 @@
 (define_expand "sgeu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(geu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (TARGET_V9)
@@ -1073,7 +1064,7 @@
 (define_expand "sleu"
   [(set (match_operand:SI 0 "intreg_operand" "")
 	(leu:SI (match_dup 1) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "
 {
   if (! TARGET_V9)
@@ -1117,7 +1108,7 @@
 	(ne:SI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1137,7 +1128,7 @@
 	(neg:SI (ne:SI (match_operand:SI 1 "register_operand" "r")
 		       (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1244,7 +1235,7 @@
 	(eq:SI (match_operand:SI 1 "register_operand" "r")
 	       (const_int 0)))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1264,7 +1255,7 @@
 	(neg:SI (eq:SI (match_operand:SI 1 "register_operand" "r")
 		       (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1376,7 +1367,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "r")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1386,7 +1377,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
@@ -1399,7 +1390,7 @@
 		  (ne:SI (match_operand:SI 1 "register_operand" "r")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1409,7 +1400,7 @@
 		  (ne:SI (match_operand:SI 1 "register_operand" "")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (minus:SI (match_dup 2)
@@ -1422,7 +1413,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "r")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1432,7 +1423,7 @@
 			(const_int 0))
 		 (match_operand:SI 2 "register_operand" "")))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (plus:SI (geu:SI (reg:CC 100) (const_int 0))
@@ -1445,7 +1436,7 @@
 		  (eq:SI (match_operand:SI 1 "register_operand" "r")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   "#"
   [(set_attr "length" "2")])
 
@@ -1455,7 +1446,7 @@
 		  (eq:SI (match_operand:SI 1 "register_operand" "")
 			 (const_int 0))))
    (clobber (reg:CC 100))]
-  "! TARGET_LIVE_G0"
+  ""
   [(set (reg:CC_NOOV 100) (compare:CC_NOOV (neg:SI (match_dup 1))
 					   (const_int 0)))
    (set (match_dup 0) (minus:SI (match_dup 2)
@@ -1469,7 +1460,7 @@
 (define_insn "*sltu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ltu:SI (reg:CC 100) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "addx\\t%%g0, 0, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1477,7 +1468,7 @@
 (define_insn "*neg_sltu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (ltu:SI (reg:CC 100) (const_int 0))))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, 0, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1487,7 +1478,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(minus:SI (neg:SI (ltu:SI (reg:CC 100) (const_int 0)))
 		  (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, %1, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1496,7 +1487,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (plus:SI (ltu:SI (reg:CC 100) (const_int 0))
 			 (match_operand:SI 1 "arith_operand" "rI"))))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, %1, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1504,7 +1495,7 @@
 (define_insn "*sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(geu:SI (reg:CC 100) (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subx\\t%%g0, -1, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1512,7 +1503,7 @@
 (define_insn "*neg_sgeu_insn"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (geu:SI (reg:CC 100) (const_int 0))))]
-  "! TARGET_LIVE_G0"
+  ""
   "addx\\t%%g0, -1, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -1525,7 +1516,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(plus:SI (ltu:SI (reg:CC 100) (const_int 0))
 		 (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
+  ""
   "addx\\t%%g0, %1, %0"
   [(set_attr "type" "misc")
    (set_attr "length" "1")])
@@ -2118,7 +2109,6 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      /* This checks TARGET_LIVE_G0 for us.  */
       if (reg_or_0_operand (operands[1], QImode))
 	goto movqi_is_ok;
 
@@ -2179,7 +2169,6 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      /* This checks TARGET_LIVE_G0 for us.  */
       if (reg_or_0_operand (operands[1], HImode))
 	goto movhi_is_ok;
 
@@ -2267,7 +2256,6 @@
   /* Handle sets of MEM first.  */
   if (GET_CODE (operands[0]) == MEM)
     {
-      /* This checks TARGET_LIVE_G0 for us.  */
       if (reg_or_0_operand (operands[1], SImode))
 	goto movsi_is_ok;
 
@@ -2326,15 +2314,6 @@
   ;
 }")
 
-;; Special LIVE_G0 pattern to obtain zero in a register.
-(define_insn "*movsi_zero_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (match_operand:SI 1 "zero_operand" "J"))]
-  "TARGET_LIVE_G0"
-  "and\\t%0, 0, %0"
-  [(set_attr "type" "binary")
-   (set_attr "length" "1")])
-
 ;; This is needed to show CSE exactly which bits are set
 ;; in a 64-bit register by sethi instructions.
 (define_insn "*movsi_const64_special"
@@ -2973,56 +2952,10 @@
 
 ;; Floating point move insns
 
-(define_insn "*movsf_insn_novis_liveg0"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m")
-	(match_operand:SF 1 "input_operand"         "f,G,Q,*rR,S,m,m,f,*r"))]
-  "(TARGET_FPU && ! TARGET_VIS && TARGET_LIVE_G0)
-   && (register_operand (operands[0], SFmode)
-       || register_operand (operands[1], SFmode))"
-  "*
-{
-  if (GET_CODE (operands[1]) == CONST_DOUBLE
-      && (which_alternative == 2
-          || which_alternative == 3
-          || which_alternative == 4))
-    {
-      REAL_VALUE_TYPE r;
-      long i;
-
-      REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]);
-      REAL_VALUE_TO_TARGET_SINGLE (r, i);
-      operands[1] = GEN_INT (i);
-    }
-
-  switch (which_alternative)
-    {
-    case 0:
-      return \"fmovs\\t%1, %0\";
-    case 1:
-      return \"and\\t%0, 0, %0\";
-    case 2:
-      return \"sethi\\t%%hi(%a1), %0\";
-    case 3:
-      return \"mov\\t%1, %0\";
-    case 4:
-      return \"#\";
-    case 5:
-    case 6:
-      return \"ld\\t%1, %0\";
-    case 7:
-    case 8:
-      return \"st\\t%1, %0\";
-    default:
-      abort();
-    }
-}"
-  [(set_attr "type" "fpmove,move,move,move,*,load,fpload,fpstore,store")
-   (set_attr "length" "1")])
-
-(define_insn "*movsf_insn_novis_noliveg0"
+(define_insn "*movsf_insn_novis"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=f,*r,*r,*r,*r,*r,f,m,m")
 	(match_operand:SF 1 "input_operand"         "f,G,Q,*rR,S,m,m,f,*rG"))]
-  "(TARGET_FPU && ! TARGET_VIS && ! TARGET_LIVE_G0)
+  "(TARGET_FPU && ! TARGET_VIS)
    && (register_operand (operands[0], SFmode)
        || register_operand (operands[1], SFmode)
        || fp_zero_operand (operands[1], SFmode))"
@@ -3203,7 +3136,7 @@
   if (GET_CODE (operands[0]) == MEM)
     {
       if (register_operand (operands[1], SFmode)
-	  || (! TARGET_LIVE_G0 && fp_zero_operand (operands[1], SFmode)))
+	  || fp_zero_operand (operands[1], SFmode))
 	goto movsf_is_ok;
 
       if (! reload_in_progress)
@@ -3245,7 +3178,7 @@
 (define_insn "*clear_dfp"
   [(set (match_operand:DF 0 "memory_operand" "=m")
         (match_operand:DF 1 "fp_zero_operand" ""))]
-  "! TARGET_LIVE_G0 && TARGET_V9"
+  "TARGET_V9"
   "stx\\t%%g0, %0"
   [(set_attr "type" "store")
    (set_attr "length" "1")])
@@ -3622,7 +3555,7 @@
 (define_insn "*clear_tfp"
   [(set (match_operand:TF 0 "memory_operand" "=m")
         (match_operand:TF 1 "fp_zero_operand" ""))]
-  "! TARGET_LIVE_G0 && TARGET_V9"
+  "TARGET_V9"
   "#"
   [(set_attr "type" "fpmove")
    (set_attr "length" "2")])
@@ -3630,7 +3563,7 @@
 (define_split
   [(set (match_operand:TF 0 "memory_operand" "=m")
         (match_operand:TF 1 "fp_zero_operand" ""))]
-  "! TARGET_LIVE_G0 && TARGET_V9 && reload_completed"
+  "TARGET_V9 && reload_completed"
   [(set (subreg:DF (match_dup 0) 0) (match_dup 1))
    (set (subreg:DF (match_dup 0) 8) (match_dup 1))]
   "
@@ -4606,7 +4539,7 @@
   [(set (reg:CC 100)
 	(compare:CC (zero_extend:SI (match_operand:QI 0 "register_operand" "r"))
 		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "andcc\\t%0, 0xff, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -4615,7 +4548,7 @@
   [(set (reg:CC 100)
 	(compare:CC (match_operand:QI 0 "register_operand" "r")
 		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "andcc\\t%0, 0xff, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -4690,7 +4623,7 @@
   [(set (reg:CC 100)
 	(compare:CC (subreg:QI (match_operand:SI 0 "register_operand" "r") 0)
 		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "andcc\\t%0, 0xff, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -4915,11 +4848,10 @@
 			  (match_operand:SI 1 "small_int_or_double" "n")
 			  (match_operand:SI 2 "small_int_or_double" "n"))
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0
-   && ((GET_CODE (operands[2]) == CONST_INT
-        && INTVAL (operands[2]) > 19)
-       || (GET_CODE (operands[2]) == CONST_DOUBLE
-           && CONST_DOUBLE_LOW (operands[2]) > 19))"
+  "(GET_CODE (operands[2]) == CONST_INT
+    && INTVAL (operands[2]) > 19)
+   || (GET_CODE (operands[2]) == CONST_DOUBLE
+       && CONST_DOUBLE_LOW (operands[2]) > 19)"
   "*
 {
   int len = (GET_CODE (operands[1]) == CONST_INT
@@ -5685,7 +5617,7 @@
 	(compare:CC_NOOV (plus:SI (match_operand:SI 0 "arith_operand" "%r")
 				  (match_operand:SI 1 "arith_operand" "rI"))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "addcc\\t%0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -5884,7 +5816,7 @@
 	(compare:CC_NOOV (minus:SI (match_operand:SI 0 "reg_or_0_operand" "rJ")
 				   (match_operand:SI 1 "arith_operand" "rI"))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subcc\\t%r0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -6174,7 +6106,7 @@
 	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
@@ -6185,7 +6117,7 @@
 	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (match_operand:SI 2 "register_operand" "r"))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "smul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
@@ -6348,7 +6280,7 @@
 	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
@@ -6359,7 +6291,7 @@
 	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
 			       (match_operand:SI 2 "uns_small_int" ""))
 		      (const_int 32))))]
-  "TARGET_HARD_MUL32 && ! TARGET_LIVE_G0"
+  "TARGET_HARD_MUL32"
   "umul\\t%1, %2, %%g0\\n\\trd\\t%%y, %0"
   [(set_attr "length" "2")])
 
@@ -6449,7 +6381,7 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(udiv:SI (match_operand:SI 1 "reg_or_nonsymb_mem_operand" "")
 		 (match_operand:SI 2 "input_operand" "")))]
-  "(TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) && ! TARGET_LIVE_G0"
+  "TARGET_V8 || TARGET_DEPRECATED_V8_INSNS"
   "")
 
 (define_insn "udivsi3_sp32"
@@ -6458,7 +6390,7 @@
 		 (match_operand:SI 2 "input_operand" "rI,m,r")))]
   "(TARGET_V8
     || TARGET_DEPRECATED_V8_INSNS)
-   && TARGET_ARCH32 && ! TARGET_LIVE_G0"
+   && TARGET_ARCH32"
   "*
 {
   output_asm_insn (\"wr\\t%%g0, %%g0, %%y\", operands);
@@ -6496,9 +6428,8 @@
 		    (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
 	(udiv:SI (match_dup 1) (match_dup 2)))]
-  "(TARGET_V8
-    || TARGET_DEPRECATED_V8_INSNS)
-   && ! TARGET_LIVE_G0"
+  "TARGET_V8
+   || TARGET_DEPRECATED_V8_INSNS"
   "*
 {
   if (TARGET_V9)
@@ -6952,7 +6883,7 @@
 			    [(match_operand:SI 0 "arith_operand" "%r")
 			     (match_operand:SI 1 "arith_operand" "rI")])
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "%A2cc\\t%0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -7003,7 +6934,7 @@
 	 (not:SI (xor:SI (match_operand:SI 0 "reg_or_0_operand" "%rJ")
 			 (match_operand:SI 1 "arith_operand" "rI")))
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "xnorcc\\t%r0, %1, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -7052,7 +6983,7 @@
 			    [(not:SI (match_operand:SI 0 "arith_operand" "rI"))
 			     (match_operand:SI 1 "reg_or_0_operand" "rJ")])
 	 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "%B2cc\\t%r1, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -7124,8 +7055,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(neg:DI (match_operand:DI 1 "register_operand" "r")))
    (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && ! TARGET_LIVE_G0"
+  "TARGET_ARCH32"
   "#"
   [(set_attr "type" "unary")
    (set_attr "length" "2")])
@@ -7134,8 +7064,7 @@
   [(set (match_operand:DI 0 "register_operand" "")
         (neg:DI (match_operand:DI 1 "register_operand" "")))
    (clobber (reg:CC 100))]
-  "! TARGET_ARCH64
-   && ! TARGET_LIVE_G0
+  "TARGET_ARCH32
    && reload_completed"
   [(parallel [(set (reg:CC_NOOV 100)
                    (compare:CC_NOOV (minus:SI (const_int 0) (match_dup 5))
@@ -7156,28 +7085,10 @@
   [(set_attr "type" "unary")
    (set_attr "length" "1")])
 
-(define_expand "negsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (neg:SI (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_LIVE_G0)
-    {
-      rtx zero_reg = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
-      emit_insn (gen_rtx_SET (VOIDmode, operands[0],
-                                      gen_rtx_MINUS (SImode, zero_reg,
-                                                             operands[1])));
-      DONE;
-    }
-}")
-
-(define_insn "*negsi2_not_liveg0"
+(define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
-  "! TARGET_LIVE_G0"
+        (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
+  ""
   "sub\\t%%g0, %1, %0"
   [(set_attr "type" "unary")
    (set_attr "length" "1")])
@@ -7186,7 +7097,7 @@
   [(set (reg:CC_NOOV 100)
 	(compare:CC_NOOV (neg:SI (match_operand:SI 0 "arith_operand" "rI"))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subcc\\t%%g0, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -7206,7 +7117,7 @@
 			 (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI (match_dup 1)))]
-  "! TARGET_LIVE_G0"
+  ""
   "subcc\\t%%g0, %1, %0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -7269,53 +7180,21 @@
   [(set_attr "type" "unary,fp")
    (set_attr "length" "1")])
 
-(define_expand "one_cmplsi2"
-  [(set (match_operand:SI 0 "register_operand" "")
-        (not:SI (match_operand:SI 1 "arith_operand" "")))]
-  ""
-  "
-{
-  if (TARGET_LIVE_G0
-      && GET_CODE (operands[1]) == CONST_INT)
-    {
-      rtx zero_reg = gen_reg_rtx (SImode);
-
-      emit_insn (gen_rtx_SET (VOIDmode, zero_reg, const0_rtx));
-      emit_insn (gen_rtx_SET (VOIDmode,
-                              operands[0],
-                              gen_rtx_NOT (SImode,
-                                           gen_rtx_XOR (SImode,
-                                                        zero_reg,
-                                                        operands[1]))));
-      DONE;
-    }
-}")
-
-(define_insn "*one_cmplsi2_not_liveg0"
+(define_insn "one_cmplsi2"
   [(set (match_operand:SI 0 "register_operand" "=r,d")
 	(not:SI (match_operand:SI 1 "arith_operand" "rI,d")))]
-  "! TARGET_LIVE_G0"
+  ""
   "@
   xnor\\t%%g0, %1, %0
   fnot1s\\t%1, %0"
   [(set_attr "type" "unary,fp")
    (set_attr "length" "1,1")])
 
-(define_insn "*one_cmplsi2_liveg0"
-  [(set (match_operand:SI 0 "register_operand" "=r,d")
-	(not:SI (match_operand:SI 1 "arith_operand" "r,d")))]
-  "TARGET_LIVE_G0"
-  "@
-  xnor\\t%1, 0, %0
-  fnot1s\\t%1, %0"
-  [(set_attr "type" "unary,fp")
-   (set_attr "length" "1,1")])
-
 (define_insn "*cmp_cc_not"
   [(set (reg:CC 100)
 	(compare:CC (not:SI (match_operand:SI 0 "arith_operand" "rI"))
 		    (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "xnorcc\\t%%g0, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -7335,7 +7214,7 @@
 		    (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
 	(not:SI (match_dup 1)))]
-  "! TARGET_LIVE_G0"
+  ""
   "xnorcc\\t%%g0, %1, %0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -8053,7 +7932,7 @@
 	(compare:CC_NOOV (ashift:SI (match_operand:SI 0 "register_operand" "r")
 				    (const_int 1))
 			 (const_int 0)))]
-  "! TARGET_LIVE_G0"
+  ""
   "addcc\\t%0, %0, %%g0"
   [(set_attr "type" "compare")
    (set_attr "length" "1")])
@@ -8954,8 +8833,6 @@
   "TARGET_SPARCLITE || TARGET_SPARCLET"
   "*
 {
-  if (TARGET_LIVE_G0)
-    output_asm_insn (\"and %%g0,0,%%g0\", operands);
   return \"sub %%g0,%1,%0\;and %0,%1,%0\;scan %0,0,%0\;mov 32,%2\;sub %2,%0,%0\;sra %0,31,%2\;and %2,31,%2\;add %2,%0,%0\";
 }"
   [(set_attr "type" "multi")
@@ -9130,7 +9007,7 @@
   [(set (match_operand:QI 0 "restore_operand" "")
 	(match_operand:QI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9147,7 +9024,7 @@
   [(set (match_operand:HI 0 "restore_operand" "")
 	(match_operand:HI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9164,7 +9041,7 @@
   [(set (match_operand:SI 0 "restore_operand" "")
 	(match_operand:SI 1 "arith_operand" "rI"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9185,7 +9062,7 @@
   [(set (match_operand:SF 0 "restore_operand" "=r")
 	(match_operand:SF 1 "register_operand" "r"))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9197,12 +9074,26 @@
 }"
   [(set_attr "type" "multi")])
 
+(define_insn "*return_df_no_fpu"
+  [(set (match_operand:DF 0 "restore_operand" "=r")
+	(match_operand:DF 1 "register_operand" "r"))
+   (return)]
+  "! TARGET_EPILOGUE && TARGET_ARCH64"
+  "*
+{
+  if (IN_OR_GLOBAL_P (operands[1]))
+    return \"return\\t%%i7+8\\n\\tmov\\t%Y1, %Y0\";
+  else
+    return \"ret\;restore %%g0, %1, %Y0\";
+}"
+  [(set_attr "type" "multi")])
+
 (define_insn "*return_addsi"
   [(set (match_operand:SI 0 "restore_operand" "")
 	(plus:SI (match_operand:SI 1 "register_operand" "r")
 		 (match_operand:SI 2 "arith_operand" "rI")))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0"
+  "! TARGET_EPILOGUE"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
@@ -9222,7 +9113,7 @@
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:SI 2 "immediate_operand" "in")))
    (return)]
-  "! TARGET_EPILOGUE && ! TARGET_LIVE_G0 && ! TARGET_CM_MEDMID"
+  "! TARGET_EPILOGUE && ! TARGET_CM_MEDMID"
   "*
 {
   if (! TARGET_ARCH64 && current_function_returns_struct)
--- gcc/config/sparc/sparc.h.jj	Fri Feb 18 16:39:17 2000
+++ gcc/config/sparc/sparc.h	Tue Feb 22 16:30:45 2000
@@ -518,19 +518,15 @@ extern int target_flags;
 #define TARGET_STACK_BIAS (target_flags & MASK_STACK_BIAS)
 
 /* Non-zero means %g0 is a normal register.
-   We still clobber it as necessary, but we can't rely on it always having
-   a zero value.
-   We don't bother to support this in true 64 bit mode.  */
+   No longer supported.  */
 #define MASK_LIVE_G0 0x100000
-#define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
+#define TARGET_LIVE_G0 0
 
 /* Non-zero means the cpu has broken `save' and `restore' insns, only
    the trivial versions work (save %g0,%g0,%g0; restore %g0,%g0,%g0).
-   We assume the environment will properly handle or otherwise avoid
-   trouble associated with an interrupt occurring after the `save' or trap
-   occurring during it.  */
+   No longer supported.  */
 #define MASK_BROKEN_SAVERESTORE 0x200000
-#define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)
+#define TARGET_BROKEN_SAVERESTORE 0
 
 /* Non-zero means -m{,no-}fpu was passed on the command line.  */
 #define MASK_FPU_SET 0x400000
@@ -1033,8 +1029,6 @@ do								\
       fixed_regs[5] = 1;					\
     else if (TARGET_ARCH64 && fixed_regs[5] == 2)		\
       fixed_regs[5] = 0;					\
-    if (TARGET_LIVE_G0)						\
-      fixed_regs[0] = 0;					\
     if (! TARGET_V9)						\
       {								\
 	int regno;						\
@@ -3361,7 +3355,6 @@ do {									\
 {"uns_arith_operand", {SUBREG, REG, CONST_INT}},			\
 {"clobbered_register", {REG}},						\
 {"input_operand", {SUBREG, REG, CONST_INT, MEM, CONST}},		\
-{"zero_operand", {CONST_INT}},						\
 {"const64_operand", {CONST_INT, CONST_DOUBLE}},				\
 {"const64_high_operand", {CONST_INT, CONST_DOUBLE}},
 
--- gcc/config/sparc/sparc.c.jj	Mon Feb 21 08:18:25 2000
+++ gcc/config/sparc/sparc.c	Tue Feb 22 16:30:45 2000
@@ -369,8 +369,7 @@ v9_regcmp_p (code)
 /* Operand constraints.  */
 
 /* Return non-zero only if OP is a register of mode MODE,
-   or const0_rtx.  Don't allow const0_rtx if TARGET_LIVE_G0 because
-   %g0 may contain anything.  */
+   or const0_rtx.  */
 
 int
 reg_or_0_operand (op, mode)
@@ -379,8 +378,6 @@ reg_or_0_operand (op, mode)
 {
   if (register_operand (op, mode))
     return 1;
-  if (TARGET_LIVE_G0)
-    return 0;
   if (op == const0_rtx)
     return 1;
   if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
@@ -1124,16 +1121,6 @@ clobbered_register (op, mode)
   return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
 }
 
-/* Return 1 if OP is const0_rtx, used for TARGET_LIVE_G0 insns.  */
-
-int
-zero_operand (op, mode)
-     rtx op;
-     enum machine_mode mode ATTRIBUTE_UNUSED;
-{
-  return op == const0_rtx;
-}
-
 /* Return 1 if OP is a valid operand for the source of a move insn.  */
 
 int
@@ -2361,12 +2348,6 @@ eligible_for_epilogue_delay (trial, slot
   if (get_attr_length (trial) != 1)
     return 0;
 
-  /* If %g0 is live, there are lots of things we can't handle.
-     Rather than trying to find them all now, let's punt and only
-     optimize things as necessary.  */
-  if (TARGET_LIVE_G0)
-    return 0;
-    
   /* If there are any call-saved registers, we should scan TRIAL if it
      does not reference them.  For now just make it easy.  */
   if (num_gfregs)
@@ -2383,11 +2364,6 @@ eligible_for_epilogue_delay (trial, slot
       return 0;
     }
 
-  /* If only trivial `restore' insns work, nothing can go in the
-     delay slot.  */
-  else if (TARGET_BROKEN_SAVERESTORE)
-    return 0;
-
   pat = PATTERN (trial);
 
   /* Otherwise, only operations which can be done in tandem with
@@ -3324,7 +3300,7 @@ output_function_prologue (file, size, le
 
   if (actual_fsize == 0)
     /* do nothing.  */ ;
-  else if (! leaf_function && ! TARGET_BROKEN_SAVERESTORE)
+  else if (! leaf_function)
     {
       if (actual_fsize <= 4096)
 	fprintf (file, "\tsave\t%%sp, -%d, %%sp\n", actual_fsize);
@@ -3339,26 +3315,6 @@ output_function_prologue (file, size, le
 	  fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
 	}
     }
-  else if (! leaf_function && TARGET_BROKEN_SAVERESTORE)
-    {
-      /* We assume the environment will properly handle or otherwise avoid
-	 trouble associated with an interrupt occurring after the `save' or
-	 trap occurring during it.  */
-      fprintf (file, "\tsave\n");
-
-      if (actual_fsize <= 4096)
-	fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize);
-      else if (actual_fsize <= 8192)
-	{
-	  fprintf (file, "\tadd\t%%fp, -4096, %%sp\n");
-	  fprintf (file, "\tadd\t%%fp, -%d, %%sp\n", actual_fsize - 4096);
-	}
-      else
-	{
-	  build_big_number (file, -actual_fsize, "%g1");
-	  fprintf (file, "\tadd\t%%fp, %%g1, %%sp\n");
-	}
-    }
   else /* leaf function */
     {
       if (actual_fsize <= 4096)
@@ -5614,8 +5570,7 @@ print_operand (file, x, code)
     {
       fputc ('[', file);
 	/* Poor Sun assembler doesn't understand absolute addressing.  */
-      if (CONSTANT_P (XEXP (x, 0))
-	  && ! TARGET_LIVE_G0)
+      if (CONSTANT_P (XEXP (x, 0)))
 	fputs ("%g0+", file);
       output_address (XEXP (x, 0));
       fputc (']', file);
@@ -6640,12 +6595,6 @@ sparc_flat_eligible_for_epilogue_delay (
   rtx pat = PATTERN (trial);
 
   if (get_attr_length (trial) != 1)
-    return 0;
-
-  /* If %g0 is live, there are lots of things we can't handle.
-     Rather than trying to find them all now, let's punt and only
-     optimize things as necessary.  */
-  if (TARGET_LIVE_G0)
     return 0;
 
   if (! reg_mentioned_p (stack_pointer_rtx, pat)
--- gcc/config/sparc/splet.h.jj	Fri Feb 18 16:39:19 2000
+++ gcc/config/sparc/splet.h	Tue Feb 22 16:30:45 2000
@@ -26,6 +26,12 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_DEFAULT
 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_EPILOGUE)
 
+#undef TARGET_LIVE_G0
+#define TARGET_LIVE_G0 (target_flags & MASK_LIVE_G0)
+
+#undef TARGET_BROKEN_SAVERESTORE
+#define TARGET_BROKEN_SAVERESTORE (target_flags & MASK_BROKEN_SAVERESTORE)
+
 /* -mlive-g0 is only supported on the sparclet.  */
 #undef SUBTARGET_SWITCHES
 #define SUBTARGET_SWITCHES \
--- gcc/config/sparc/linux-aout.h.jj	Fri Feb 18 16:39:07 2000
+++ gcc/config/sparc/linux-aout.h	Tue Feb 22 16:30:45 2000
@@ -109,12 +109,6 @@ Boston, MA 02111-1307, USA.  */
 #define LONG_DOUBLE_TYPE_SIZE 128
 #endif
 
-/* No weird SPARC variants on Linux */
-#undef TARGET_LIVE_G0
-#define TARGET_LIVE_G0			0
-#undef TARGET_BROKEN_SAVERESTORE
-#define TARGET_BROKEN_SAVERESTORE	0
-
 /* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
    traps available which can get and set the condition codes
    reliably.  */
--- gcc/config/sparc/linux.h.jj	Fri Feb 18 16:39:07 2000
+++ gcc/config/sparc/linux.h	Tue Feb 22 16:30:45 2000
@@ -238,12 +238,6 @@ do {									\
 #define LONG_DOUBLE_TYPE_SIZE 128
 #endif
 
-/* No weird SPARC variants on Linux */
-#undef TARGET_LIVE_G0
-#define TARGET_LIVE_G0			0
-#undef TARGET_BROKEN_SAVERESTORE
-#define TARGET_BROKEN_SAVERESTORE	0
-
 /* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
    traps available which can get and set the condition codes
    reliably.  */
--- gcc/config/sparc/linux64.h.jj	Fri Feb 18 16:39:07 2000
+++ gcc/config/sparc/linux64.h	Tue Feb 22 16:30:45 2000
@@ -350,12 +350,6 @@ do {									\
 
 /* #define DWARF_OFFSET_SIZE PTR_SIZE */
 
-/* No weird SPARC variants on Linux */
-#undef TARGET_LIVE_G0
-#define TARGET_LIVE_G0			0
-#undef TARGET_BROKEN_SAVERESTORE
-#define TARGET_BROKEN_SAVERESTORE	0
-
 #if TARGET_ARCH32
 /* Override MACHINE_STATE_{SAVE,RESTORE} because we have special
    traps available which can get and set the condition codes
--- gcc/config/sparc/sol2.h.jj	Fri Feb 18 16:39:08 2000
+++ gcc/config/sparc/sol2.h	Tue Feb 22 16:30:45 2000
@@ -204,12 +204,6 @@ Boston, MA 02111-1307, USA.  */
   fixunsdfdi_libfunc							\
     = init_one_libfunc (TARGET_ARCH64 ? "__dtoul" : "__dtoull")
 
-/* No weird SPARC variants on Solaris */
-#undef TARGET_LIVE_G0
-#define TARGET_LIVE_G0	0
-#undef TARGET_BROKEN_SAVERESTORE
-#define TARGET_BROKEN_SAVERESTORE 0
-
 /* Solaris allows 64 bit out and global registers in 32 bit mode.
    sparc_override_options will disable V8+ if not generating V9 code.  */
 #undef TARGET_DEFAULT

Cheers,
    Jakub
___________________________________________________________________
Jakub Jelinek | jakub@redhat.com | http://sunsite.mff.cuni.cz/~jj
Linux version 2.3.47 on a sparc64 machine (1343.49 BogoMips)
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