patch for case 102820

[Jeffrey A Law]

  In message < Pine.SOL.3.91.1000215170531.25073b-100000@canuck.cygnus.com >you w
rite:
  > Hi,
  > 
  > I am working on a branch vr4xxxx of mips architecture, but in the CR 
  > they mentioned problem in eCos. 
  > 
  > The customer is complaining about bc1* instructions. These instructions 
  > should be separated by alteast one instruction from the preceding 
  > floating point compare instruction. 
  > 
  > When i looked at the manual Vr4300 Microprocessor User's Manual for bc1f 
  > and bc1t instruction, both have the following defination.
  > 
  >    The result of the comparison is sampled while the instruction 
  > immediately preceding is executed, at least one instruciton must be 
  > inserted in between the floating point compare instruction and this 
  > instruction.  
  > 
  > 
  > Since bc1* insn are generated immediately after the compare instructions 
  > i have added a nop just before generating bc1f and bc1t insns. 
  > 
  > Here is the patch for this fix. Please let me know if this is fine. 
  > 
  > While debugging this code, i figured out we already have some in mips.c 
  > which basically inserts nop before bc1* instructions. Who ever is owning 
  > please let me know is this the right place to fix this bug or my fix is 
  > fine.
Addition of NOPs for MIPS ports without cpu interlocks is handled in the
assembler, not the compiler.  SO the proper place to fix this is in the
assembler.

jeff