ia64 32-shift tweek

Richard Henderson rth@cygnus.com
Sun Aug 20 11:54:00 GMT 2000


My last patch ignored possible garbage at the top of the 
SImode shift count.  For reasons I don't understand, Intel
doesn't use just the low N bits for the shift, but the 
whole register.  So we've got to get rid of the garbage.


r~


        * config/ia64/ia64.md (ashlsi3): Zero extend the shift count.
        (ashrsi3, lshrsi3): Likewise.

Index: ia64.md
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/ia64/ia64.md,v
retrieving revision 1.69.2.10
diff -c -p -d -r1.69.2.10 ia64.md
*** ia64.md	2000/08/19 19:10:33	1.69.2.10
--- ia64.md	2000/08/20 18:47:22
***************
*** 2012,2021 ****
  ;; ::
  ;; ::::::::::::::::::::
  
! (define_insn "ashlsi3"
    [(set (match_operand:SI 0 "register_operand" "=r,r,r")
  	(ashift:SI (match_operand:SI 1 "register_operand" "r,r,r")
! 		   (match_operand:SI 2 "reg_or_5bit_operand" "R,n,r")))]
    ""
    "@
     shladd %0 = %1, %2, r0
--- 2012,2038 ----
  ;; ::
  ;; ::::::::::::::::::::
  
! (define_expand "ashlsi3"
!   [(set (match_operand:SI 0 "register_operand" "")
! 	(ashift:SI (match_operand:SI 1 "register_operand" "")
! 		   (match_operand:SI 2 "reg_or_5bit_operand" "")))]
!   ""
!   "
! {
!   if (GET_CODE (operands[2]) != CONST_INT)
!     {
!       /* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED?  Now
! 	 we've got to get rid of stray bits outside the SImode register.  */
!       rtx subshift = gen_reg_rtx (DImode);
!       emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
!       operands[2] = subshift;
!     }
! }")
! 
! (define_insn "*ashlsi3_internal"
    [(set (match_operand:SI 0 "register_operand" "=r,r,r")
  	(ashift:SI (match_operand:SI 1 "register_operand" "r,r,r")
! 		   (match_operand:DI 2 "reg_or_5bit_operand" "R,n,r")))]
    ""
    "@
     shladd %0 = %1, %2, r0
***************
*** 2036,2044 ****
  			 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
    else
      {
        emit_insn (gen_extendsidi2 (subtarget, operands[1]));
!       emit_insn (gen_ashrdi3 (subtarget, subtarget,
! 			      gen_lowpart (DImode, operands[2])));
      }
    emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
    DONE;
--- 2053,2062 ----
  			 GEN_INT (32 - INTVAL (operands[2])), operands[2]));
    else
      {
+       rtx subshift = gen_reg_rtx (DImode);
        emit_insn (gen_extendsidi2 (subtarget, operands[1]));
!       emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
!       emit_insn (gen_ashrdi3 (subtarget, subtarget, subshift));
      }
    emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
    DONE;
***************
*** 2057,2065 ****
  			  GEN_INT (32 - INTVAL (operands[2])), operands[2]));
    else
      {
        emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
!       emit_insn (gen_lshrdi3 (subtarget, subtarget,
! 			      gen_lowpart (DImode, operands[2])));
      }
    emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
    DONE;
--- 2075,2084 ----
  			  GEN_INT (32 - INTVAL (operands[2])), operands[2]));
    else
      {
+       rtx subshift = gen_reg_rtx (DImode);
        emit_insn (gen_zero_extendsidi2 (subtarget, operands[1]));
!       emit_insn (gen_zero_extendsidi2 (subshift, operands[2]));
!       emit_insn (gen_lshrdi3 (subtarget, subtarget, subshift));
      }
    emit_move_insn (gen_lowpart (DImode, operands[0]), subtarget);
    DONE;


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