ia64 promote_mode
Richard Henderson
rth@cygnus.com
Fri Aug 11 16:50:00 GMT 2000
On Fri, Aug 11, 2000 at 03:31:33PM -0700, Richard Henderson wrote:
> * config/ia64/ia64.h (PROMOTE_MODE): Only extend to SImode.
This is really part to of the preceeding patch. I'd not had
things properly tidied up in my local tree though.
Given that we're not generating DImode variables, we shouldn't
be generating DImode arithmetic when not needed either.
r~
* config/ia64/ia64.md (addsi3): Remove expander.
(subsi3, mulsi3, negsi2, one_cmplsi2): Likewise.
(*addsi3_shladd): New.
Index: ia64.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/ia64/ia64.md,v
retrieving revision 1.31
diff -c -p -d -r1.31 ia64.md
*** ia64.md 2000/08/11 23:10:10 1.31
--- ia64.md 2000/08/11 23:34:32
***************
*** 1087,1119 ****
;; ::
;; ::::::::::::::::::::
! ;; We handle 32-bit arithmetic just like the alpha port does.
!
! (define_expand "addsi3"
! [(set (match_operand:SI 0 "register_operand" "")
! (plus:SI (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "reg_or_22bit_operand" "")))]
! ""
! "
! {
! if (optimize)
! {
! rtx op1 = gen_lowpart (DImode, operands[1]);
! rtx op2 = gen_lowpart (DImode, operands[2]);
!
! if (! cse_not_expected)
! {
! rtx tmp = gen_reg_rtx (DImode);
! emit_insn (gen_adddi3 (tmp, op1, op2));
! emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
! }
! else
! emit_insn (gen_adddi3 (gen_lowpart (DImode, operands[0]), op1, op2));
! DONE;
! }
! }")
!
! (define_insn "*addsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "%r,r,a")
(match_operand:SI 2 "reg_or_22bit_operand" "r,I,J")))]
--- 1087,1093 ----
;; ::
;; ::::::::::::::::::::
! (define_insn "addsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
(plus:SI (match_operand:SI 1 "register_operand" "%r,r,a")
(match_operand:SI 2 "reg_or_22bit_operand" "r,I,J")))]
***************
*** 1142,1172 ****
"add %0 = %1, %1, 1"
[(set_attr "type" "A")])
! (define_expand "subsi3"
! [(set (match_operand:SI 0 "register_operand" "")
! (minus:SI (match_operand:SI 1 "reg_or_8bit_operand" "")
! (match_operand:SI 2 "register_operand" "")))]
""
! "
! {
! if (optimize)
! {
! rtx op1 = gen_lowpart (DImode, operands[1]);
! rtx op2 = gen_lowpart (DImode, operands[2]);
!
! if (! cse_not_expected)
! {
! rtx tmp = gen_reg_rtx (DImode);
! emit_insn (gen_subdi3 (tmp, op1, op2));
! emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
! }
! else
! emit_insn (gen_subdi3 (gen_lowpart (DImode, operands[0]), op1, op2));
! DONE;
! }
! }")
! (define_insn "*subsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_8bit_operand" "rK")
(match_operand:SI 2 "register_operand" "r")))]
--- 1116,1131 ----
"add %0 = %1, %1, 1"
[(set_attr "type" "A")])
! (define_insn "*addsi3_shladd"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
! (match_operand:SI 2 "shladd_operand" "n"))
! (match_operand:SI 3 "register_operand" "r")))]
""
! "shladd %0 = %1, %S2, %3"
! [(set_attr "type" "A")])
! (define_insn "subsi3"
[(set (match_operand:SI 0 "register_operand" "=r")
(minus:SI (match_operand:SI 1 "reg_or_8bit_operand" "rK")
(match_operand:SI 2 "register_operand" "r")))]
***************
*** 1182,1214 ****
"sub %0 = %2, %1, 1"
[(set_attr "type" "A")])
- (define_expand "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "")
- (mult:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "register_operand" "")))]
- ""
- "
- {
- if (optimize)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
- rtx op2 = gen_lowpart (DImode, operands[2]);
-
- if (! cse_not_expected)
- {
- rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_muldi3 (tmp, op1, op2));
- emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
- }
- else
- emit_insn (gen_muldi3 (gen_lowpart (DImode, operands[0]), op1, op2));
- DONE;
- }
- }")
-
;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
! (define_insn "*mulsi3_internal"
[(set (match_operand:SI 0 "register_operand" "=f")
(mult:SI (match_operand:SI 1 "register_operand" "f")
(match_operand:SI 2 "nonmemory_operand" "f")))]
--- 1141,1149 ----
"sub %0 = %2, %1, 1"
[(set_attr "type" "A")])
;; ??? Could add maddsi3 patterns patterned after the madddi3 patterns.
! (define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=f")
(mult:SI (match_operand:SI 1 "register_operand" "f")
(match_operand:SI 2 "nonmemory_operand" "f")))]
***************
*** 1216,1244 ****
"xma.l %0 = %1, %2, f0%B0"
[(set_attr "type" "F")])
! (define_expand "negsi2"
! [(set (match_operand:SI 0 "register_operand" "")
! (neg:SI (match_operand:SI 1 "register_operand" "")))]
! ""
! "
! {
! if (optimize)
! {
! rtx op1 = gen_lowpart (DImode, operands[1]);
!
! if (! cse_not_expected)
! {
! rtx tmp = gen_reg_rtx (DImode);
! emit_insn (gen_negdi2 (tmp, op1));
! emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
! }
! else
! emit_insn (gen_negdi2 (gen_lowpart (DImode, operands[0]), op1));
! DONE;
! }
! }")
!
! (define_insn "*negsi2_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
""
--- 1151,1157 ----
"xma.l %0 = %1, %2, f0%B0"
[(set_attr "type" "F")])
! (define_insn "negsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(neg:SI (match_operand:SI 1 "register_operand" "r")))]
""
***************
*** 1970,1976 ****
;; ::::::::::::::::::::
;; ::
! ;; :: 32 Bit Integer Logical operations
;; ::
;; ::::::::::::::::::::
--- 1883,1889 ----
;; ::::::::::::::::::::
;; ::
! ;; :: 32 bit Integer Logical operations
;; ::
;; ::::::::::::::::::::
***************
*** 1987,2026 ****
;; (zero_extend (and (not A) B)) in combine.
;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
;; one_cmplsi2 pattern.
-
- (define_expand "one_cmplsi2"
- [(set (match_operand:SI 0 "register_operand" "")
- (not:SI (match_operand:SI 1 "register_operand" "")))]
- ""
- "
- {
- if (optimize)
- {
- rtx op1 = gen_lowpart (DImode, operands[1]);
! if (! cse_not_expected)
! {
! rtx tmp = gen_reg_rtx (DImode);
! emit_insn (gen_one_cmpldi2 (tmp, op1));
! emit_move_insn (operands[0], gen_lowpart (SImode, tmp));
! }
! else
! emit_insn (gen_one_cmpldi2 (gen_lowpart (DImode, operands[0]), op1));
! DONE;
! }
! }")
!
! (define_insn "*one_cmplsi2_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
"andcm %0 = -1, %1"
[(set_attr "type" "A")])
-
;; ::::::::::::::::::::
;; ::
! ;; :: 64 Bit Integer Logical operations
;; ::
;; ::::::::::::::::::::
--- 1900,1916 ----
;; (zero_extend (and (not A) B)) in combine.
;; Or maybe fix this by adding andsi3/iorsi3/xorsi3 patterns like the
;; one_cmplsi2 pattern.
! (define_insn "one_cmplsi2"
[(set (match_operand:SI 0 "register_operand" "=r")
(not:SI (match_operand:SI 1 "register_operand" "r")))]
""
"andcm %0 = -1, %1"
[(set_attr "type" "A")])
;; ::::::::::::::::::::
;; ::
! ;; :: 64 bit Integer Logical operations
;; ::
;; ::::::::::::::::::::
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