sparc output reload fix
Richard Henderson
rth@cygnus.com
Sun Oct 31 23:33:00 GMT 1999
I have no idea how I managed to bootstrap twice today with
the previous patch in my tree. A fresh build tree replicates
the problem reported building gmon-sol2.c.
r~
Fri Oct 15 01:20:52 1999 Richard Henderson <rth@cygnus.com>
* sparc.md (movsf_const_intreg): Revert last constraint change.
(movdf_const_intreg_sp32): Likewise.
Index: sparc.md
===================================================================
RCS file: /cvs/cvsfiles/devo/gcc/config/sparc/sparc.md,v
retrieving revision 1.96
diff -c -p -d -r1.96 sparc.md
*** sparc.md 1999/10/15 00:39:08 1.96
--- sparc.md 1999/10/15 08:19:49
***************
*** 2753,2760 ****
(set_attr "length" "1")])
(define_insn "*movsf_const_intreg"
! [(set (match_operand:SF 0 "register_operand" "=fr")
! (match_operand:SF 1 "const_double_operand" "F"))]
"TARGET_FPU"
"*
{
--- 2753,2760 ----
(set_attr "length" "1")])
(define_insn "*movsf_const_intreg"
! [(set (match_operand:SF 0 "register_operand" "=f,r")
! (match_operand:SF 1 "const_double_operand" "m,F"))]
"TARGET_FPU"
"*
{
***************
*** 2921,2934 ****
(set_attr "length" "1")])
(define_insn "*movdf_const_intreg_sp32"
! [(set (match_operand:DF 0 "register_operand" "=e,r")
! (match_operand:DF 1 "const_double_operand" "T,F"))]
"TARGET_FPU && ! TARGET_ARCH64"
"@
ldd\\t%1, %0
#"
[(set_attr "type" "move")
! (set_attr "length" "1,2")])
;; Now that we redo life analysis with a clean slate after
;; instruction splitting for sched2 this can work.
--- 2921,2935 ----
(set_attr "length" "1")])
(define_insn "*movdf_const_intreg_sp32"
! [(set (match_operand:DF 0 "register_operand" "=e,e,r")
! (match_operand:DF 1 "const_double_operand" "T,o,F"))]
"TARGET_FPU && ! TARGET_ARCH64"
"@
ldd\\t%1, %0
+ #
#"
[(set_attr "type" "move")
! (set_attr "length" "1,2,2")])
;; Now that we redo life analysis with a clean slate after
;; instruction splitting for sched2 this can work.
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