Renaming -mshort-load-bytes
Nick Clifton
nickc@cygnus.com
Sun Nov 21 07:24:00 GMT 1999
Hi Guys,
OK here is the patch to rename the -mshort-load-bytes option. After
applying this patch the gcc --help output looks like this:
...
Target specific options:
...
-malignment-traps Do not issue unaligned word loads as the MMU will trap
...
And gcc.info now contains the following:
`-malignment-traps'
This option specifies that the target processor has an MMU which
is set to generate a fault if an unaligned word access is
generated. Since this is an undesirable event, the compiler will
take steps to prevent generating code that could cause this. The
only circumstances under which the compiler would normally
generate an unaligned word access is if the target CPU does not
support a halfword load instruction and a halfword sized quantity
is being loaded into memory from a non-word aligned address. In
this case the compiler would normally generate a word load
instruction, relying upon a feature of the ARM architecture to
correctly rotate the loaded value into the destination register.
If this option is enabled however, the compiler will no longer do
this. Instead it will issue two byte load instructions and then
'or' the values together. This option only has an effect on code
generated for ARM architectures earlier than ARMv4 since the newer
architecures have a halfword load instruction.
Note that this option does not cope with the pathalogical situation
where a programmer deliberatly attempts to access a word quantity
using a non-word aligned pointer.
`-mno-alignment-traps'
Allows the compiler to use word load instructions to load halfword
quantities, which is more efficient than generating two byte load
instructions. This is the default for most ARM toolchain targets.
This option only has an effect on code generated for ARM
architectures earlier than ARMv4.
Shall I apply this patch to the sources ?
Cheers
Nick
1999-11-21 Nick Clifton <nickc@cygnus.com>
* invoke.texi (ARM Options): Replace -mshort-load-bytes with
-malignment-traps.
(arm.h): Replace -mshort-load-bytes with -malignment-traps.
(arm.c): Replace TARGET_SHORT_BY_BYTES with TARGET_MMU_TRAPS.
(arm.md): Replace TARGET_SHORT_BY_BYTES with TARGET_MMU_TRAPS.
Index: invoke.texi
===================================================================
RCS file: /cvs/gcc/egcs/gcc/invoke.texi,v
retrieving revision 1.152
diff -p -r1.152 invoke.texi
*** invoke.texi 1999/11/19 00:23:01 1.152
--- invoke.texi 1999/11/21 15:17:45
*************** in the following sections.
*** 261,267 ****
-mapcs-reentrant -mno-apcs-reentrant
-msched-prolog -mno-sched-prolog
-mlittle-endian -mbig-endian -mwords-little-endian
! -mshort-load-bytes -mno-short-load-bytes -mshort-load-words -mno-short-load-words
-msoft-float -mhard-float -mfpe
-mthumb-interwork -mno-thumb-interwork
-mcpu= -march= -mfpe=
--- 261,267 ----
-mapcs-reentrant -mno-apcs-reentrant
-msched-prolog -mno-sched-prolog
-mlittle-endian -mbig-endian -mwords-little-endian
! -malignment-traps
-msoft-float -mhard-float -mfpe
-mthumb-interwork -mno-thumb-interwork
-mcpu= -march= -mfpe=
*************** option should only be used if you requir
*** 4372,4397 ****
big-endian ARM processors generated by versions of the compiler prior to
2.8.
@item -mshort-load-bytes
@kindex -mshort-load-bytes
! Do not try to load half-words (eg @samp{short}s) by loading a word from
! an unaligned address. For some targets the MMU is configured to trap
! unaligned loads; use this option to generate code that is safe in these
! environments.
@item -mno-short-load-bytes
@kindex -mno-short-load-bytes
! Use unaligned word loads to load half-words (eg @samp{short}s). This
! option produces more efficient code, but the MMU is sometimes configured
! to trap these instructions.
@item -mshort-load-words
@kindex -mshort-load-words
! This is a synonym for @samp{-mno-short-load-bytes}.
@item -mno-short-load-words
@kindex -mno-short-load-words
! This is a synonym for @samp{-mshort-load-bytes}.
@item -mbsd
@kindex -mbsd
--- 4372,4422 ----
big-endian ARM processors generated by versions of the compiler prior to
2.8.
+ @item -malignment-traps
+ @kindex -malignment-traps
+ This option specifies that the target processor has an MMU which is set
+ to generate a fault if an unaligned word access is generated. Since
+ this is an undesirable event, the compiler will take steps to prevent
+ generating code that could cause this. The only circumstances under
+ which the compiler would normally generate an unaligned word access is
+ if the target CPU does not support a halfword load instruction and a
+ halfword sized quantity is being loaded into memory from a non-word
+ aligned address. In this case the compiler would normally generate a
+ word load instruction, relying upon a feature of the ARM architecture to
+ correctly rotate the loaded value into the destination register. If
+ this option is enabled however, the compiler will no longer do this.
+ Instead it will issue two byte load instructions and then 'or' the
+ values together. This option only has an effect on code generated for
+ ARM architectures earlier than ARMv4 since the newer architecures have
+ a halfword load instruction.
+
+ Note that this option does not cope with the pathalogical situation
+ where a programmer deliberatly attempts to access a word quantity using
+ a non-word aligned pointer.
+
+ @item -mno-alignment-traps
+ @kindex -mno-alignment-traps
+ Allows the compiler to use word load instructions to load halfword
+ quantities, which is more efficient than generating two byte load
+ instructions. This is the default for most ARM toolchain targets. This
+ option only has an effect on code generated for ARM architectures
+ earlier than ARMv4.
+
@item -mshort-load-bytes
@kindex -mshort-load-bytes
! This is a depreciated alias for @samp{-malignment-traps}.
@item -mno-short-load-bytes
@kindex -mno-short-load-bytes
! This is a depreciated alias for @samp{-mno-alignment-traps}.
@item -mshort-load-words
@kindex -mshort-load-words
! This is a depreciated alias for @samp{-mno-alignment-traps}.
@item -mno-short-load-words
@kindex -mno-short-load-words
! This is a depreciated alias for @samp{-malignment-traps}.
@item -mbsd
@kindex -mbsd
Index: config/arm/arm.h
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.h,v
retrieving revision 1.54
diff -p -r1.54 arm.h
*** arm.h 1999/11/12 13:38:38 1.54
--- arm.h 1999/11/21 15:17:46
*************** Unrecognized value in TARGET_CPU_DEFAULT
*** 285,293 ****
This is equivalent to -fpic. */
#define ARM_FLAG_APCS_REENT (1 << 6)
! /* Nonzero if the MMU will trap unaligned word accesses, so shorts must be
! loaded byte-at-a-time. */
! #define ARM_FLAG_SHORT_BYTE (1 << 7)
/* Nonzero if all floating point instructions are missing (and there is no
emulator either). Generate function calls for all ops in this case. */
--- 285,293 ----
This is equivalent to -fpic. */
#define ARM_FLAG_APCS_REENT (1 << 6)
! /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
! be loaded using either LDRH or LDRB instructions. */
! #define ARM_FLAG_MMU_TRAPS (1 << 7)
/* Nonzero if all floating point instructions are missing (and there is no
emulator either). Generate function calls for all ops in this case. */
*************** Unrecognized value in TARGET_CPU_DEFAULT
*** 323,336 ****
#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
! /* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
! that short values should not be accessed using word load instructions
! as there is a possibility that they may not be word aligned and this
! would generate an MMU fault. On processors which do not have a 16 bit
! load instruction therefore, short values must be loaded by individual
! byte accesses rather than loading a word and then shifting the desired
! value into place. */
! #define TARGET_SHORT_BY_BYTES (target_flags & ARM_FLAG_SHORT_BYTE)
#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
--- 323,329 ----
#define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
! #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
#define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
#define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
#define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
*************** Unrecognized value in TARGET_CPU_DEFAULT
*** 369,380 ****
{"apcs-reentrant", ARM_FLAG_APCS_REENT, \
"Generate re-entrant, PIC code" }, \
{"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
! {"short-load-bytes", ARM_FLAG_SHORT_BYTE, \
! "Load shorts a byte at a time" }, \
! {"no-short-load-bytes", -ARM_FLAG_SHORT_BYTE, "" }, \
! {"short-load-words", -ARM_FLAG_SHORT_BYTE, \
! "Load words a byte at a time" }, \
! {"no-short-load-words", ARM_FLAG_SHORT_BYTE, "" }, \
{"soft-float", ARM_FLAG_SOFT_FLOAT, \
"Use library calls to perform FP operations" }, \
{"hard-float", -ARM_FLAG_SOFT_FLOAT, \
--- 362,374 ----
{"apcs-reentrant", ARM_FLAG_APCS_REENT, \
"Generate re-entrant, PIC code" }, \
{"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
! {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
! "Do not issue unaligned word loads as the MMU will trap" },\
! {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
! {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
! {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
! {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
! {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
{"soft-float", ARM_FLAG_SOFT_FLOAT, \
"Use library calls to perform FP operations" }, \
{"hard-float", -ARM_FLAG_SOFT_FLOAT, \
*************** extern int arm_is_6_or_7;
*** 540,546 ****
if (MODE == QImode) \
UNSIGNEDP = 1; \
else if (MODE == HImode) \
! UNSIGNEDP = TARGET_SHORT_BY_BYTES != 0; \
(MODE) = SImode; \
}
--- 534,540 ----
if (MODE == QImode) \
UNSIGNEDP = 1; \
else if (MODE == HImode) \
! UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
(MODE) = SImode; \
}
*************** enum reg_class
*** 1002,1008 ****
/* If we need to load shorts byte-at-a-time, then we need a scratch. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
! (((MODE) == HImode && ! arm_arch4 && TARGET_SHORT_BY_BYTES \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \
--- 996,1002 ----
/* If we need to load shorts byte-at-a-time, then we need a scratch. */
#define SECONDARY_INPUT_RELOAD_CLASS(CLASS,MODE,X) \
! (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \
Index: config/arm/arm.c
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.c,v
retrieving revision 1.72
diff -p -r1.72 arm.c
*** arm.c 1999/11/09 16:45:49 1.72
--- arm.c 1999/11/21 15:17:48
*************** gen_rotated_half_load (memref)
*** 3483,3489 ****
}
/* If we aren't allowed to generate unaligned addresses, then fail. */
! if (TARGET_SHORT_BY_BYTES
&& ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
return NULL;
--- 3483,3489 ----
}
/* If we aren't allowed to generate unaligned addresses, then fail. */
! if (TARGET_MMU_TRAPS
&& ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0)))
return NULL;
Index: config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/egcs/gcc/config/arm/arm.md,v
retrieving revision 1.38
diff -p -r1.38 arm.md
*** arm.md 1999/11/02 17:06:24 1.38
--- arm.md 1999/11/21 15:17:49
***************
*** 2441,2447 ****
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
! /* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
here because the insn below will generate an LDRH instruction
rather than an LDR instruction, so we cannot get an unaligned
word access. */
--- 2441,2447 ----
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
! /* Note: We do not have to worry about TARGET_MMU_TRAPS
here because the insn below will generate an LDRH instruction
rather than an LDR instruction, so we cannot get an unaligned
word access. */
***************
*** 2449,2455 ****
gen_rtx_ZERO_EXTEND (SImode, operands[1])));
DONE;
}
! if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_movhi_bytes (operands[0], operands[1]));
DONE;
--- 2449,2455 ----
gen_rtx_ZERO_EXTEND (SImode, operands[1])));
DONE;
}
! if (TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_movhi_bytes (operands[0], operands[1]));
DONE;
***************
*** 2549,2555 ****
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
! /* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
here because the insn below will generate an LDRH instruction
rather than an LDR instruction, so we cannot get an unaligned
word access. */
--- 2549,2555 ----
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
{
! /* Note: We do not have to worry about TARGET_MMU_TRAPS
here because the insn below will generate an LDRH instruction
rather than an LDR instruction, so we cannot get an unaligned
word access. */
***************
*** 2558,2564 ****
DONE;
}
! if (TARGET_SHORT_BY_BYTES && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
DONE;
--- 2558,2564 ----
DONE;
}
! if (TARGET_MMU_TRAPS && GET_CODE (operands[1]) == MEM)
{
emit_insn (gen_extendhisi2_mem (operands[0], operands[1]));
DONE;
***************
*** 3184,3196 ****
}
else if (! arm_arch4)
{
! /* Note: We do not have to worry about TARGET_SHORT_BY_BYTES
for v4 and up architectures because LDRH instructions will
be used to access the HI values, and these cannot generate
unaligned word access faults in the MMU. */
if (GET_CODE (operands[1]) == MEM)
{
! if (TARGET_SHORT_BY_BYTES)
{
rtx base;
rtx offset = const0_rtx;
--- 3184,3196 ----
}
else if (! arm_arch4)
{
! /* Note: We do not have to worry about TARGET_MMU_TRAPS
for v4 and up architectures because LDRH instructions will
be used to access the HI values, and these cannot generate
unaligned word access faults in the MMU. */
if (GET_CODE (operands[1]) == MEM)
{
! if (TARGET_MMU_TRAPS)
{
rtx base;
rtx offset = const0_rtx;
***************
*** 3289,3295 ****
[(set (match_operand:SI 0 "s_register_operand" "=r")
(rotate:SI (match_operand:SI 1 "offsettable_memory_operand" "o")
(const_int 16)))]
! "! TARGET_SHORT_BY_BYTES"
"*
{
rtx ops[2];
--- 3289,3295 ----
[(set (match_operand:SI 0 "s_register_operand" "=r")
(rotate:SI (match_operand:SI 1 "offsettable_memory_operand" "o")
(const_int 16)))]
! "! TARGET_MMU_TRAPS"
"*
{
rtx ops[2];
***************
*** 3373,3379 ****
(match_operand:HI 1 "general_operand" "rI,K,m"))]
"! arm_arch4
&& ! BYTES_BIG_ENDIAN
! && ! TARGET_SHORT_BY_BYTES
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1])))"
--- 3373,3379 ----
(match_operand:HI 1 "general_operand" "rI,K,m"))]
"! arm_arch4
&& ! BYTES_BIG_ENDIAN
! && ! TARGET_MMU_TRAPS
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1])))"
***************
*** 3389,3395 ****
(match_operand:HI 1 "general_operand" "rI,K,m"))]
"! arm_arch4
&& BYTES_BIG_ENDIAN
! && ! TARGET_SHORT_BY_BYTES
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1])))"
--- 3389,3395 ----
(match_operand:HI 1 "general_operand" "rI,K,m"))]
"! arm_arch4
&& BYTES_BIG_ENDIAN
! && ! TARGET_MMU_TRAPS
&& (GET_CODE (operands[1]) != CONST_INT
|| const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1])))"
***************
*** 3406,3412 ****
(rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0)
(const_int 16)))]
"BYTES_BIG_ENDIAN
! && ! TARGET_SHORT_BY_BYTES"
"ldr%?\\t%0, %1\\t%@ movhi_bigend"
[(set_attr "type" "load")
(set_attr "pool_range" "4096")])
--- 3406,3412 ----
(rotate:SI (subreg:SI (match_operand:HI 1 "memory_operand" "m") 0)
(const_int 16)))]
"BYTES_BIG_ENDIAN
! && ! TARGET_MMU_TRAPS"
"ldr%?\\t%0, %1\\t%@ movhi_bigend"
[(set_attr "type" "load")
(set_attr "pool_range" "4096")])
***************
*** 3414,3420 ****
(define_insn "*movhi_bytes"
[(set (match_operand:HI 0 "s_register_operand" "=r,r")
(match_operand:HI 1 "arm_rhs_operand" "rI,K"))]
! "TARGET_SHORT_BY_BYTES"
"@
mov%?\\t%0, %1\\t%@ movhi
mvn%?\\t%0, #%B1\\t%@ movhi")
--- 3414,3420 ----
(define_insn "*movhi_bytes"
[(set (match_operand:HI 0 "s_register_operand" "=r,r")
(match_operand:HI 1 "arm_rhs_operand" "rI,K"))]
! "TARGET_MMU_TRAPS"
"@
mov%?\\t%0, %1\\t%@ movhi
mvn%?\\t%0, #%B1\\t%@ movhi")
***************
*** 3436,3442 ****
[(parallel [(match_operand:HI 0 "s_register_operand" "=r")
(match_operand:HI 1 "reload_memory_operand" "o")
(match_operand:DI 2 "s_register_operand" "=&r")])]
! "TARGET_SHORT_BY_BYTES"
"
arm_reload_in_hi (operands);
DONE;
--- 3436,3442 ----
[(parallel [(match_operand:HI 0 "s_register_operand" "=r")
(match_operand:HI 1 "reload_memory_operand" "o")
(match_operand:DI 2 "s_register_operand" "=&r")])]
! "TARGET_MMU_TRAPS"
"
arm_reload_in_hi (operands);
DONE;
***************
*** 5932,5938 ****
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1) (match_dup 2)))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_SHORT_BY_BYTES
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
--- 5932,5938 ----
(set (match_operand:SI 0 "s_register_operand" "=r")
(plus:SI (match_dup 1) (match_dup 2)))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
***************
*** 5947,5953 ****
(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))]
"(!BYTES_BIG_ENDIAN)
! && ! TARGET_SHORT_BY_BYTES
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
--- 5947,5953 ----
(set (match_operand:SI 0 "s_register_operand" "=r")
(minus:SI (match_dup 1) (match_dup 2)))]
"(!BYTES_BIG_ENDIAN)
! && ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& (GET_CODE (operands[2]) != REG
***************
*** 6085,6091 ****
(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
(match_dup 1)))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_SHORT_BY_BYTES
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
--- 6085,6091 ----
(plus:SI (match_op_dup 2 [(match_dup 3) (match_dup 4)])
(match_dup 1)))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
***************
*** 6102,6108 ****
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
(match_dup 4)])))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_SHORT_BY_BYTES
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
--- 6102,6108 ----
(minus:SI (match_dup 1) (match_op_dup 2 [(match_dup 3)
(match_dup 4)])))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_MMU_TRAPS
&& REGNO (operands[0]) != FRAME_POINTER_REGNUM
&& REGNO (operands[1]) != FRAME_POINTER_REGNUM
&& REGNO (operands[3]) != FRAME_POINTER_REGNUM"
***************
*** 6149,6155 ****
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_SHORT_BY_BYTES
&& REGNO(operands[0]) != REGNO(operands[1])
&& (GET_CODE (operands[2]) != REG
|| REGNO(operands[0]) != REGNO (operands[2]))"
--- 6149,6155 ----
(set (match_dup 1)
(plus:SI (match_dup 1) (match_operand:SI 2 "index_operand" "rJ")))]
"(! BYTES_BIG_ENDIAN)
! && ! TARGET_MMU_TRAPS
&& REGNO(operands[0]) != REGNO(operands[1])
&& (GET_CODE (operands[2]) != REG
|| REGNO(operands[0]) != REGNO (operands[2]))"
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