x86 ashlsi3 improvements

[Jan Hubicka]

>   > You need to take into account important property of lea - it is executed
>   > in operand fetch pass, so its operands have memory adress behaviour - they
>   > need to be ready one cycle before lea is executed otherwise AGI stall
>   > happends.
> Yes.  I'm aware of AGI stalls.
> 
> One thing we can do to mitigate this would be to use a shift instruction if the
> instruction is believed to be the first in an issue bundle.  This can be
> determined by looking at the mode of the insn.  If it is not TImode, then the
> insn is expected to be the 1st insn in an issue bundle, meaning it is expected
> to issue into the U pipe and we should use sal over lea.
This sounds like interesting idea. I will try to implement this soon. The mode is set
by scheduler? I didn't know about this feature. I will try to dig out my pentium
MD_SCHED reorder macros and try how well this can be used. (with the MD_SCHED macros
the TImode flag should more accurately represent the U pipe).

We will still need to modify agi stall funtions to recognize lea stall IMO...
> 
> This will avoid many of the AGI stalls, and over time as the x86 port improves
> in terms of Pentium scheduling this scheme will improve along the way too.
BTW I've heard that Richard is working on the rewrite of i386 port. Is that true?

Honza
> 
> jeff

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