PATCH: Add pa8000 scheduling
Jerry Quinn
jquinn@nortelnetworks.com
Fri Mar 5 08:22:00 GMT 1999
This patch adds a basis for further work on HP PA8000 support. I've added
8000 as a -mschedule= option for the pa port. I created an initial go at the
machine description by cloning the 7100LC machine description and modifying
the delays to match what I've found in the references on HP's site. See the
following URL:
http://www.hp.com/ahp/framed/technology/micropro/
In addition, I've added a -march= option for specifying the instruction set,
although it doesn't currently do anything.
--
Jerry Quinn Tel: (514) 761-8737
jquinn@nortelnetworks.com Fax: (514) 761-8505
Speech Recognition Research
Here is the Changlog entry:
Fri Mar 5 10:02:37 EST 1999 Jerry Quinn <jquinn@nortelnetworks.com>
* pa.h (processor_type): Add PROCESSOR_8000 symbol.
(ISSUE_RATE): Return 4 for PROCESSOR_8000.
(architecture_type): Define.
(pa_arch_string): Reference.
(pa_arch): Reference.
(TARGET_OPTIONS): Add -march= option.
(MASK_PA_1_1): New. Alias for MASK_SNAKE
(TARGET_PA_1_1): New. Alias for TARGET_SNAKE
* pa.c (pa_arch): Define.
(pa_arch_string): Define.
(override_options): Add 8000 as -mschedule= option. Add -march=
option.
* pa.md (attr cpu): Add 8000.
(function_unit): Add initial pa8000 description.
diff -c orig/gcc/config/pa/pa.c egcs-19990228/gcc/config/pa/pa.c
*** orig/gcc/config/pa/pa.c Mon Mar 1 11:14:56 1999
--- egcs-19990228/gcc/config/pa/pa.c Thu Mar 4 15:03:53 1999
***************
*** 58,63 ****
--- 58,69 ----
/* String to hold which cpu we are scheduling for. */
char *pa_cpu_string;
+ /* Which architecture we are generating insns for. */
+ enum architecture_type pa_arch;
+
+ /* String to the architecture. */
+ char *pa_arch_string;
+
/* Set by the FUNCTION_PROFILER macro. */
int hp_profile_labelno;
***************
*** 118,126 ****
pa_cpu_string = "7200";
pa_cpu = PROCESSOR_7200;
}
else
{
! warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100 and 7100LC and 7200\n", pa_cpu_string);
}
if (flag_pic && TARGET_PORTABLE_RUNTIME)
--- 124,173 ----
pa_cpu_string = "7200";
pa_cpu = PROCESSOR_7200;
}
+ else if (! strcmp (pa_cpu_string, "8000"))
+ {
+ pa_cpu_string = "8000";
+ pa_cpu = PROCESSOR_8000;
+ }
+ else
+ {
+ warning ("Unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, and 8000\n", pa_cpu_string);
+ }
+
+ /* Default architecture corresponds to pa_cpu */
+ if (! strcmp (pa_arch_string, "1.0"))
+ {
+ pa_arch = ARCH_PA_1_0;
+ }
+ else if (! strcmp (pa_arch_string, "1.1"))
+ {
+ pa_arch = ARCH_PA_1_1;
+ }
+ else if (! strcmp (pa_arch_string, "2.0"))
+ {
+ pa_arch = ARCH_PA_2_0;
+ }
+ else if (pa_arch_string == NULL)
+ {
+ switch (pa_cpu) {
+ case PROCESSOR_700:
+ pa_arch = ARCH_PA_1_0;
+ break;
+ case PROCESSOR_7100:
+ case PROCESSOR_7100LC:
+ case PROCESSOR_7200:
+ pa_arch = ARCH_PA_1_1;
+ break;
+ case PROCESSOR_8000:
+ pa_arch = ARCH_PA_2_0;
+ break;
+ }
+ }
else
{
! warning ("Unknown -march= option (%s).\n"
! "Valid options are 1.0, 1.1, and 2.0\n",
! pa_arch_string);
}
if (flag_pic && TARGET_PORTABLE_RUNTIME)
diff -c orig/gcc/config/pa/pa.h egcs-19990228/gcc/config/pa/pa.h
*** orig/gcc/config/pa/pa.h Mon Mar 1 11:14:56 1999
--- egcs-19990228/gcc/config/pa/pa.h Thu Mar 4 14:28:38 1999
***************
*** 39,45 ****
PROCESSOR_700,
PROCESSOR_7100,
PROCESSOR_7100LC,
! PROCESSOR_7200
};
/* For -mschedule= option. */
--- 39,46 ----
PROCESSOR_700,
PROCESSOR_7100,
PROCESSOR_7100LC,
! PROCESSOR_7200,
! PROCESSOR_8000
};
/* For -mschedule= option. */
***************
*** 49,56 ****
#define pa_cpu_attr ((enum attr_cpu)pa_cpu)
/* The 700 can only issue a single insn at a time.
! The 7XXX processors can issue two insns at a time. */
! #define ISSUE_RATE (pa_cpu == PROCESSOR_700 ? 1 : 2)
/* Print subsidiary information on the compiler version in use. */
--- 50,71 ----
#define pa_cpu_attr ((enum attr_cpu)pa_cpu)
/* The 700 can only issue a single insn at a time.
! The 7XXX processors can issue two insns at a time.
! The 8000 can issue 4 insns at a time. */
! #define ISSUE_RATE (pa_cpu == PROCESSOR_700 ? 1 : (pa_cpu < PROCESSOR_8000 ? 2 : 4))
!
! /* Which architecture to generate insns for. */
!
! enum architecture_type
! {
! ARCH_PA_1_0,
! ARCH_PA_1_1,
! ARCH_PA_2_0
! };
!
! /* For -march= option. */
! extern char *pa_arch_string;
! extern enum architecture_type pa_arch;
/* Print subsidiary information on the compiler version in use. */
***************
*** 64,69 ****
--- 79,87 ----
#define MASK_SNAKE 1
#define TARGET_SNAKE (target_flags & MASK_SNAKE)
+ #define MASK_PA_1_1 MASK_SNAKE
+ #define TARGET_PA_1_1 TARGET_SNAKE
+
/* Disable all FP registers (they all become fixed). This may be necessary
for compiling kernels which perform lazy context switching of FP regs.
***************
*** 175,181 ****
#define TARGET_OPTIONS \
{ \
! { "schedule=", &pa_cpu_string }\
}
#define OVERRIDE_OPTIONS override_options ()
--- 193,200 ----
#define TARGET_OPTIONS \
{ \
! { "schedule=", &pa_cpu_string }, \
! { "arch=", &pa_arch_string }\
}
#define OVERRIDE_OPTIONS override_options ()
diff -c orig/gcc/config/pa/pa.md egcs-19990228/gcc/config/pa/pa.md
*** orig/gcc/config/pa/pa.md Mon Mar 1 11:14:56 1999
--- egcs-19990228/gcc/config/pa/pa.md Thu Mar 4 16:29:05 1999
***************
*** 43,49 ****
;;
;; FIXME: Add 800 scheduling for completeness?
! (define_attr "cpu" "700,7100,7100LC,7200" (const (symbol_ref "pa_cpu_attr")))
;; Length (in # of insns).
(define_attr "length" ""
--- 43,49 ----
;;
;; FIXME: Add 800 scheduling for completeness?
! (define_attr "cpu" "700,7100,7100LC,7200,8000" (const (symbol_ref "pa_cpu_attr")))
;; Length (in # of insns).
(define_attr "length" ""
***************
*** 349,354 ****
--- 349,443 ----
;; I don't have detailed information on the PA7200 FP pipeline, so I
;; treat it just like the 7100LC pipeline.
;; Similarly for the multi-issue fake units.
+
+ ;; ----- PA8000 scheduling
+ ;; This is the space to start putting PA8000 series processor info. At the
+ ;; moment, it is basically a clone of the 7100LC stuff except that an 8000
+ ;; appears to have 2 of everything. Also different latencies
+
+ ;; Memory. Disregarding Cache misses, memory loads and stores take
+ ;; two cycles. Any special cases are handled in pa_adjust_cost.
+
+ ;; pa8000 has two separate instruction ALU's that can each issue one address
+ ;; per cycle. I'm guessing that it is like the 7200 in not having store-store
+ ;; penalty.
+ (define_function_unit "pa8000memory" 2 0
+ (and (eq_attr "type" "load,fpload")
+ (eq_attr "cpu" "8000")) 2 0)
+
+ (define_function_unit "pa8000memory" 2 0
+ (and (eq_attr "type" "store,fpstore")
+ (eq_attr "cpu" "8000")) 2 0)
+
+ ;; NOTE: the following comment is copied from the 7100LC above. Not knowing
+ ;; anything about this, I think it means that it pretends to define 3 virtual
+ ;; FPU's modeling that adds and mults can be chained together. Just my
+ ;; guess.
+
+ ;; The 8000 has three floating-point unit types: ALU, MUL, and DIV.
+ ;; Note divides and sqrt flops lock the div/sqrt unit until the flop is
+ ;; finished.
+ ;; Timings:
+ ;; Instruction Time Unit Minimum Distance (unit contention)
+ ;; fcpy 3 ALU 1
+ ;; fabs 3 ALU 1
+ ;; fadd 3 ALU 1
+ ;; fsub 3 ALU 1
+ ;; fcmp 3 ALU 1
+ ;; fcnv 3 ALU 1
+ ;; fmpyadd,sgl 3 ALU,MPY 1
+ ;; fmpyadd,dbl 3 ALU,MPY 1
+ ;; fmpysub,sgl 3 ALU,MPY 1
+ ;; fmpysub,dbl 3 ALU,MPY 1
+ ;; fmpycfxt,sgl 3 ALU,MPY 1
+ ;; fmpycfxt,dbl 3 ALU,MPY 1
+ ;; fmpy,sgl 3 MPY 1
+ ;; fmpy,dbl 3 MPY 1
+ ;; fmpyi 3 MPY 1
+ ;; fdiv,sgl 17 DIV 17
+ ;; fdiv,dbl 31 DIV 31
+ ;; fsqrt,sgl 17 DIV 17
+ ;; fsqrt,dbl 31 DIV 31
+
+ (define_function_unit "pa8000fp_alu" 2 0
+ (and (eq_attr "type" "fpcc,fpalu")
+ (eq_attr "cpu" "8000")) 3 1)
+ (define_function_unit "pa8000fp_mpy" 2 0
+ (and (eq_attr "type" "fpmulsgl,fpmuldbl")
+ (eq_attr "cpu" "8000")) 3 1)
+
+ ;; I tried these with 2 1 to indicate that the division wasn't pipelined, but
+ ;; it didn't work
+ (define_function_unit "pa8000fp_div" 2 0
+ (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
+ (eq_attr "cpu" "8000")) 17 17)
+ (define_function_unit "pa8000fp_div" 2 0
+ (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
+ (eq_attr "cpu" "8000")) 31 31)
+
+ ;; Define the various functional units for dual-issue.
+
+ ;; There's two real floating point units. However, the div/sqrt can be run in
+ ;; parallel to the mul/add within each unit. Only one insn can be issued per
+ ;; cycle, though. I don't know the correct way to model it.
+ (define_function_unit "pa8000flop" 2 1
+ (and
+ (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
+ (eq_attr "cpu" "8000")) 1 1)
+
+ ;; Shifts and memory ops actually execute in one of the integer
+ ;; ALUs, but we can't really model that.
+ (define_function_unit "pa8000shiftmem" 2 1
+ (and
+ (eq_attr "type" "shift,nullshift,load,fpload,store,fpstore")
+ (eq_attr "cpu" "8000")) 1 1)
+
+ ;; We have four basic ALUs. (twice 7100LC)
+ (define_function_unit "pa8000alu" 4 2
+ (and
+ (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
+ (eq_attr "cpu" "8000")) 1 1)
+
;; Compare instructions.
More information about the Gcc-patches
mailing list