mulhi patch for new_ia32_branch

[Jan Hubicka]

Hi
This patch avoids promoting of qimode multiply to himode. It also fix the
length attribute setting there.
Note that it depends on my genrecog fix.

Sat Jul 24 21:08:20 EDT 1999  Jan Hubicka  <hubicka@freesoft.cz>
	* i386.md (mulsi): Fix length attribute
	(mulhi): Likewise
	New combiner patterns to avoid matching of optimizes mulqihi
	pattern by mulhi, new splitters.

*** /root/i386old2/i386.md	Tue Jul 20 02:34:08 1999
--- i386.md	Sat Jul 24 19:00:03 1999
***************
*** 3683,3702 ****
     imul{l}\\t{%2, %0|%0, %2}
     imul{l}\\t{%2, %0|%0, %2}"
    [(set_attr "type" "imul")
!    (set_attr "length" "2,3,2")])
  
  (define_insn "mulhi3"
!   [(set (match_operand:HI 0 "register_operand" "=r,r")
! 	(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0")
! 		 (match_operand:HI 2 "general_operand" "K,g")))
     (clobber (reg:CC 17))]
    ""
    ; %%% There was a note about "Assembler has weird restrictions",
    ; concerning alternative 1 when op1 == op0.  True?
    "@
     imul{w}\\t{%2, %1, %0|%0, %1, %2}
     imul{w}\\t{%2, %0|%0, %2}"
!   [(set_attr "type" "imul")])
  
  (define_insn "umulqihi3"
    [(set (match_operand:HI 0 "register_operand" "=a")
--- 3855,3928 ----
     imul{l}\\t{%2, %0|%0, %2}
     imul{l}\\t{%2, %0|%0, %2}"
    [(set_attr "type" "imul")
!    (set_attr "length_opcode" "2,2,3")])
! 
! ;; This insn is created from mulqihi by combine when followed by move of
! ;; subreg (that is normally result of QImode multiply). 
! ;; Originally it was matched by mulhi3 pattern resulting in
! ;; unnecesary extra prefix and potential partial register stall.
! 
! ;; Promote to more general SI mode imul instruction when possible.
! ;; ??? Some CPUs may have SImode mul slower than QImode mul.
! ;; (i486 and i386?) avoid promoting here.
! (define_insn ""
!   [(set (subreg:HI (match_operand:QI 0 "register_operand" "=r,r,a") 0)
! 	(mult:HI (subreg:HI (match_operand:QI 1 "nonimmediate_operand" "%r,0,0") 0)
! 		 (subreg:HI (match_operand:QI 2 "general_operand" "K,i,qm") 0)))
!    (clobber (reg:CC 17))]
!   "! TARGET_PARTIAL_REG_STALL"
!   "#")
! 
! ;; Otherwise convert back to QImode pattern.
! (define_insn ""
!   [(set (subreg:HI (match_operand:QI 0 "register_operand" "=a") 0)
! 	(mult:HI (subreg:HI (match_operand:QI 1 "register_operand" "%0") 0)
! 		 (subreg:HI (match_operand:QI 2 "nonimmediate_operand" "qm") 0)))
!    (clobber (reg:CC 17))]
!   "TARGET_PARTIAL_REG_STALL"
!   "#")
! 
! (define_split
!   [(set (subreg:HI (match_operand:QI 0 "nonmemory_operand" "") 0)
! 	(mult:HI (subreg:HI (match_operand:QI 1 "nonmemory_operand" "") 0)
! 		 (subreg:HI (match_operand:QI 2 "aligned_operand" "") 0)))
!    (clobber (reg:CC 17))]
!   "reload_completed && ! TARGET_PARTIAL_REG_STALL"
!   [(parallel [(set (match_dup 0)
! 		   (mult:SI (match_dup 1)
! 			    (match_dup 2)))
! 	      (clobber (reg:CC 17))])]
!   "operands[0] = gen_lowpart (SImode, operands[0]);
!    operands[1] = gen_lowpart (SImode, operands[1]);
!    operands[2] = gen_lowpart (SImode, operands[2]);")
! 
! (define_split
!   [(set (subreg:HI (match_operand:QI 0 "register_operand" "") 0)
! 	(mult:HI (subreg:HI (match_operand:QI 1 "nonimmediate_operand" "") 0)
! 		 (subreg:HI (match_operand:QI 2 "general_operand" "") 0)))
!    (clobber (reg:CC 17))]
!   ""
!   [(parallel [(set (match_dup 0)
! 		   (mult:HI (zero_extend:HI (match_dup 1))
! 			    (zero_extend:HI (match_dup 2))))
! 	      (clobber (reg:CC 17))])]
!   "operands[0] = gen_lowpart (HImode, operands[0]);")
  
  (define_insn "mulhi3"
!   [(set (match_operand:HI 0 "register_operand" "=r,r,r")
! 	(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,0,0")
! 		 (match_operand:HI 2 "general_operand" "K,i,g")))
     (clobber (reg:CC 17))]
+   ; Do not match with cases handled bellow.
    ""
    ; %%% There was a note about "Assembler has weird restrictions",
    ; concerning alternative 1 when op1 == op0.  True?
    "@
     imul{w}\\t{%2, %1, %0|%0, %1, %2}
+    imul{w}\\t{%2, %0|%0, %2}
     imul{w}\\t{%2, %0|%0, %2}"
!   [(set_attr "type" "imul")
!    (set_attr "length_opcode" "2,2,3")])
  
  (define_insn "umulqihi3"
    [(set (match_operand:HI 0 "register_operand" "=a")